User`s guide

DWMBB Adapter

3.3 I/O Transactions

I/O transactions originate from a processor on the XMI and are

independent of the address translation mode.

The DWMBB uses two regions of I/O address space: XMI nodespace and

VAXBI nodespace.

The XMI nodespace, assuming a 32-bit XMI address, has the range (all in

hex) of E180 0000 + (8 0000 * XMI Node ID) through E184 01FC + (8 0000

* XMI Node ID). Not all addresses in this range are used.

The 32-Mbyte region of VAXBI I/O adapter address (or window) space is

used by XMI nodes to access VAXBI I/O address space.

The DWMBB returns a read error response (RER) to the XMI node that

makes an I/O reference to a nonexistent I/O register location. If the

DWMBB/B module receives an illegal write C/A cycle or detects a parity

error on the write C/A cycle, it aborts the transaction and informs the

DWMBB/A module that the I/O write failed. If IVINTRs are enabled, the

DWMBB/A module also issues an IVINTR to the XMI.

3.3.1 I/O References to DWMBB/A Module Registers

The DWMBB/A module latches an XMI I/O read transaction directed to

one of its internal registers when sent by an XMI commander node. Parity

is checked and, if no error is detected, it then arbitrates for the XMI

as a responder. Once the grant is received, it places the contents of the

requested register on the XMI. When the read data is successfully received

by the originating XMI node, the DWMBB/A module clears the appropriate

I/O ﬂags and is ready to accept another I/O transaction.

The DWMBB/A module latches an XMI I/O write transaction and its

associated data directed to one of its internal registers when sent by an

XMI commander. The DWMBB/A module then updates the requested

that it is ready to accept another I/O transaction.

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