User`s guide

DWMBB Adapter
3.2.4 40-Bit Address Translation (8-Kbyte Page Size)
When 40-bit address translation mode with 8-Kbyte page sizes is enabled,
the DWMBB translates the address of any DMA transaction received into
a 40-bit XMI address. All 512 Mbytes of VAXBI memory address space are
mapped, because the 64 K entries are sufficient to map the 512 Mbytes
with 8-Kbyte pages. In this mode the value loaded into the BIIC’s Starting
Address Register must be less than the value of the Ending Address
Register.
The 40-bit translation of a VAXBI DMA address using 8-Kbyte page sizes
uses VAXBI address bits <28:13> as an index into the PMRs. The validity
of the selected PFN is checked and, if good, the PFN is used to complete
the DMA address translation. The 40-bit XMI physical address is obtained
by concatenating bits PMRE<25:0> of the PFN field with VAXBI address
bits <12:0>.
The steps used for the 40-bit address translation using 8-Kbyte page sizes
are as follows:
1 Check the upper address bits: VAXBI A<29> must be zero.
2 Access PMR for PMRE: VAXBI A<28:13> is an index into the PMR to
fetch the PMRE.
3 Check PMRE valid bit: If PMRE<31> = 1, then PFN is valid; otherwise
PFN is invalid and the transaction is aborted.
4 ECC check: If no uncorrectable error, then PFN is good; otherwise
PFN is bad and the transaction is aborted.
5 Generate XMI address: Zero XMI A<39>; PMRE<26:0> XMI
A<38:13>; VAXBI A<12:0> XMI A<12:0>.
Figure 3–6 shows the 40-bit address translation using 4-Kbyte page sizes.
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