User`s guide

DWMBB Adapter
Figure 3–4 40-Bit Addressing Mode with 512-Byte Page Size
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0
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4980
VAXBI A<31:0> 0 PMR INDEX ADDRESS PAGE OFFSET
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9
PMRE PFN
XMI
A<39:0>
Bit <39> (the I/O select) is always forced to 0
LEN 0
XMI PHYSICAL ADDRESS
Access PMR for PMRE
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80
msb−p085−89
V0
Check if PFN is valid
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0
3.2.3 40-Bit Address Translation (4-Kbyte Page Size)
When 40-bit address translation mode with 4-Kbyte page sizes is enabled,
the DWMBB translates the address of any DMA transaction received
into a 40-bit XMI address. Only the first 256 Mbytes of VAXBI memory
address space are mapped, because the 64 K entries are not sufficient
to map all 512 Mbytes of VAXBI memory space. In this mode the value
loaded into the BIIC’s Ending Address Register must be within the first
256 Mbytes, and the value in the Starting Address Register must be less
than the value of the Ending Address Register.
The 40-bit translation of a VAXBI DMA address using 4-Kbyte page sizes
uses VAXBI address bits <27:12> as an index into the PMRs. These bits
select the specific PMRE that contains the required PFN. The upper
address bits of VAXBI A<29:28> must be zero. The validity of the selected
PFN is checked and, if good, the PFN is used to complete the DMA address
translation. The 40-bit XMI physical address is obtained by concatenating
bits PMRE<26:0> of the PFN field with VAXBI address bits A<11:0>.
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