User`s guide

DWMBB Adapter
3.2.2 40-Bit VAX Address Translation
The 40-bit VAX address translation mode is enabled by setting the Map
Register Enable field in the DWMBB/A Utility Register (AUTLR) bits
<19:18> to one. When in this mode the DWMBB translates the address of
any DMA transaction received from the VAXBI into a 40-bit XMI address.
Although the full 40 bits are not used, the lower 32 are used in VAX 6000
models above 500. In this mode the BIIC’s Starting Address Register (in
the DWMBB/B module) is loaded with a value of zero, and the Ending
Address Register is loaded with the address of the first longword location
of the next 32-Mbyte region, which is 200 0000 (hex). The DWMBB maps
only the first 32 Mbytes of VAXBI memory address space to XMI memory
address space, because there are not enough page map register (PMR)
entries to map all of VAXBI memory space.
This is the mode used for a VAX 6000 system when its physical address is
32 bits in length.
The translation of a VAXBI DMA address uses VAXBI A<24:9> as an
index into the PMRs. These bits select the specific page map register
entry (PMRE) that contains the required PFN. The upper VAXBI address
bits, VAXBI A<29:25>, must be zero since the DWMBB only maps the first
32 Mbytes of VAXBI memory address space. The validity of the selected
PFN is checked and, if good, the PFN is used to complete the DMA address
translation. The 40-bit XMI physical address is obtained by concatenating
the PFN field of the PMRE, bits <29:0>, with VAXBI address bits, VAXBI
A<8:0>.
The steps used for the 40-bit VAX address translation are as follows:
1 Check the upper address bits: VAXBI A<29:25> must all be zero.
2 Access PMR for PMRE: VAXBI A<24:9> is an index into the PMR to
fetch the PMRE.
3 Check PMRE valid bit: If PMRE<31> = 1, then PFN is valid; otherwise
PFN is invalid and the transaction is aborted.
4 ECC check: If no uncorrectable error, then PFN is good; otherwise
PFN is bad and the transaction is aborted.
5 Generate XMI address: Zero XMI A<39>; PMRE<29:0> XMI
A<38:9>; VAXBI A<8:0> XMI A<8:0>.
Figure 3–4 shows the 40-bit VAX address translation.
The 32-bit address translation is generated using the 40-bit address
translations. The upper eight address bits, A<39:32>, are forced to zero.
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