User`s guide

DWMBB Adapter
DWMBB address translation uses a mapping register scheme. The page
map registers (PMRs) are implemented in RAM and provide 64 K (65,536)
32-bit locations. All mapping register locations are maintained by system
software, which ensures that all required page frame numbers (PFNs)
loaded in the mapping registers are valid before any I/O device initiates a
DMA transaction.
The mapping of a VAXBI address to XMI memory address space is
controlled by the following separate functions:
• The Starting and Ending Address Registers of the BIIC, which are on
the DWMBB/B module
• The current address translation mode of the DWMBB/A module
Table 3–1 shows the DWMBB address translation modes with their
maximum amount of VAXBI memory address space that can be mapped to
XMI memory address space.
Table 3–1 VAXBI ADDRESS MAPPING
Addressing Mode
Number of
Mapping
Registers
VAXBI Memory
Address Space
Mapped
DWMBA compatibility (30 bits of VAX address) N/A 512 Mbytes
40-bit extended VAX address translation 64 K 32 Mbytes
40-bit extended address translation using 4-Kbyte page size 64 K 256 Mbytes
40-bit extended address translation using 8-Kbyte page size 64 K 512 Mbytes
The Map Register Mode Enable field of the DWMBB/A Utility Register
(AUTLR<19:17>) is used to set the address translation mode.
The DWMBA compatibility mode is the default mode, which is in
effect after power-up and XMI node reset. While in this mode, address
translation is disabled and the VAXBI memory address space is directly
mapped into the first 512 Mbytes of XMI memory space. For a VAXBI
device to address memory space greater than 512 Mbytes, the DWMBB
must be set to one of the address translation modes.
When address translation is enabled, the DWMBB performs address
translation only on DMA transactions. The access of XMI I/O address
space from nodes on the VAXBI is restricted. System software maintains
proper memory access by ensuring that valid PFN entries are in the PMRs
for any DMA transaction to be translated.
Some VAXBI transactions do not have corresponding XMI transactions and
are not supported by the DWMBB. Also, some XMI transactions do not
have corresponding VAXBI transactions and are not supported. Table 3–2
and Table 3–3 list the corresponding transactions.
3–5