User`s guide

DWMBB Adapter
The DWMBB/A module contains an XMI Corner, register files, XMI
required registers, DWMBB/A module-specific registers, page map
registers, and control sequencers for the XMI interface.
The DWMBB/B module contains a VAXBI Corner, interconnect drivers,
control sequencers to handle the control of the data transfer, status bits
to/from the DWMBB/A module’s register files and the BIIC, DWMBB/B
module-specific registers, decode logic for DMA operations, and VAXBI
clock-generation circuitry.
These two modules are connected by four cables of 30 wires each. The 120
wires make up the IBUS, which transfers data and control information
between the two modules.
The DWMBB uses I/O and DMA transactions to exchange information. I/O
transactions originate from the CPU module(s) and are presented to the
DWMBB from the XMI bus with the CPU as the XMI commander and the
DWMBB as the XMI responder.
DMA transactions originate from VAXBI nodes that select the DWMBB
as the VAXBI slave. These are read or write transactions targeted to XMI
memory space or are VAXBI-generated interrupt transactions that target a
CPU module. For DMA transactions, the DWMBB is the XMI commander
and the memory module is the XMI responder.
Write transactions, whether DMA or I/O, are always disconnected. This
means that as soon as either the CPU or the VAXBI master issues the
write, it waits for an ACK confirmation that the command and write data
was accepted but not necessarily completed at the destination. If the write
fails, a write error Implied Vector Interrupt (IVINTR) is returned.
Processors using the VAX 6000 platform use either a 30- or 32-bit physical
address. Chapter 2 describes the XMI address space. The VAXBI Options
Handbook describes the VAXBI address space. The DWMBB can be
both a master and a slave on the VAXBI. As a master, it carries out I/O
transactions requested by its XMI devices. As a slave, it responds to
VAXBI transactions that select its node.
The DWMBB has several addressing modes, two of which will be discussed
here. The adapter is capable of handling a 40-bit address, which the
XMI supports. For purposes of this book, however, references to 40-bit
addressing will be kept to a minimum to limit confusion.
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