User`s guide

The XMI
• The DWMBB being unable to complete a VAXBI-to-XMI windowed
write operation. Then the DWMBB issues a write error IVINTR
transaction to the nodes designated in the DWMBB AIVINTR
destination register. This results in system software failure.
Processor nodes also use the memory error interrupt (IPL 1D (hex))
to report other node-specific error conditions, such as potential cache
coherency problems or write buffer errors. Some of these errors might
be recoverable by software, but the processor needs to contain additional
state to identify these conditions.
In an SMP operating system, with processes migrating between processors,
an error condition might not be associated with the related process even
when the error condition can be isolated to a specific processor. Therefore,
many bus-related error conditions result in system software failure.
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