User`s guide

Contents
2–30 Hexword Data Return with Uncorrectable Read Error 2–50
2–31 Longword and Quadword Writes 2–50
2–32 Octaword Write 2–51
2–33 XMI Initialization Flowchart 2–53
2–34 Failed Hexword Write Transaction 2–78
3–1 DWMBB Adapter Block Diagram 3–2
3–2 VAXBI I/O Address Space for XMI Node 1 3–4
3–3 DWMBA Compatibility Mode Address 3–8
3–4 40-Bit Addressing Mode with 512-Byte Page Size 3–11
3–5 40-Bit Addressing Mode with 4-Kbyte Page Size 3–12
3–6 40-Bit Addressing Mode with 8-Kbyte Page Size 3–14
3–7 INTR and IDENT Formats 3–18
3–8 XMI Vector Format 3–21
3–9 VAXBI Node Vector Format 3–22
3–10 IVINTR Command Format 3–25
3–11 VAXBI Wrapped Read Transactions 3–26
3–12 Responder Request and XMI SUP L Timing 3–33
3–13 Page Map Register Organization 3–37
3–14 DWMBB Loopbacks 3–133
3–15 DWMBB/A Module Transmit Registers 3–137
3–16 DWMBB/A Module Receive Registers 3–138
3–17 Testing the DMA Transmit and Receive Registers 3–143
TABLES
1 VAX 6000 Series Documentation xiii
2 VAX 6000 Model Level Documentation xiv
3 Associated Documents xiv
1–1 VAX 6000 Platform Differences 1–2
1–2 VAX 6000 Series System Characteristics 1–3
1–3 Input Voltage 1–12
1–4 DC Power Distribution 1–13
2–1 Usable XMI Bandwidth 2–3
2–2 Data Transactions Supported by the XMI 2–6
2–3 XMI Interrupt Transactions 2–10
2–4 XMI Arbitration Lines 2–11
2–5 XMI Nodespace Addresses 2–15
2–6 XMI Registers 2–15
2–7 VAXBI Nodespace and Window Space Address Assignments 2–18
2–8 VAXBI Registers 2–19
2–9 XMI Function Codes 2–22
2–10 XMI Command Codes 2–24
2–11 XMI Transaction Length Codes 2–26
2–12 XMI Transactions 2–31
2–13 Memory Space Transactions 2–32
xi