User`s guide

The XMI

Figure 2–34 Failed Hexword Write Transaction

Missing First Data Cycle

−−−−−−−−−−−−−−−−−−−−−−−−

FUNCT

DATA

CONF

FUNCT

DATA

CONF

msb−p213−89

Missing Second Data Cycle

−−−−−−−−−−−−−−−−−−−−−−−−−

2.9.2 Error Handling

XMI commanders and responders react to error conditions as follows:

• Receivers that detect bad parity ignore the cycle.

• For WMASK and UWMASK transactions, responders ignore any write

transactions containing a sequence or parity error; that is, none of the

data at the referenced location is modiﬁed because the entire write

transaction is ignored.

• For DWMASK transactions, responders start processing the

transaction as soon as the command is received if the ownership

bit remains set. If the ownership bit does not remain set, all data

cycles are properly received.

• Responders receiving a NO ACK conﬁrmation to a read response do

not transmit further read responses associated with that transaction

within 10 XMI cycles of the NO ACK.

• Memory nodes set a lock bit if the command/address cycle of the

IREAD transaction is successfully received.

• Memory nodes do not clear a lock bit unless all write data cycles

associated with the UWMASK transaction are properly received.

• Cached processors detecting an inconsistent parity error either ﬂush

their caches or perform a machine check.

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