User`s guide

The XMI
2.9 XMI Errors
The XMI bus detects all single-bit transmission-related errors on
XMI D<63:0> L, XMI F<3:0> L, XMI ID<5:0> L, XMI P<2:0> L, and
XMI CNF lines. The XMI protocol permits XMI commanders to
recover from all transient memory space read/write transaction
errors as well as from most I/O space read/write transaction errors.
2.9.1 Error Conditions
2.9.1.1 Parity Error
To detect single-bit errors, all nodes monitor parity of the bus. Any XMI
receiver detecting bad parity ignores the cycle and returns a NO ACK
confirmation.
2.9.1.2 Inconsistent Parity Error
Under certain error conditions, such as intermittent connectors, some
nodes might detect bad parity while others compute proper parity. If the
intended target of the transaction computes good parity, then the cycle
may be ACKed (and assumed good by the commander), even if other nodes
ignore the cycle due to bad parity.
For XMI memory-space Write Mask, Unlock Write Mask, and Ownership
Read transactions, this class of error may result in cache coherency
problems due to cached processors failing to perform cache invalidates.
Processors recover from this error by having error recovery software flush
the cache (all "clean" blocks are invalidated and "owned dirty" blocks are
written back to main memory).
For IVINTR transactions, some destinations of the IVINTR transaction
may not receive the interrupt. All other XMI transactions ignore this class
of error.
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