User`s guide

XMI Registers
Failing Address Extension Register (XFAER)
Failing Address Extension Register (XFAER)
The Failing Address Extension Register logs command, address, and write
mask information (in the case of write transactions) associated with a failing
transaction. Only XMI commander nodes are required to implement this
register.
XFAER is the higher 32 bits of a 64-bit register formed by concatenating
XFADR and XFAER. For detailed information on the low order bits of the
failing address see the XFADR register.
XFADR and XFAER latch on the first XMI bus error. The following rules
govern the overwriting of the information in the registers:
• If no error information is in the registers, they are written on the first hard
or soft error.
• If soft error information is being latched, the registers are not changed on
subsequent soft errors.
• If soft error information is being latched, the registers are overwritten by a
hard error.
• If hard error information is being latched, the information is not changed
on subsequent errors.
Setting of the following XBER bits are hard errors and force the latching of
XFADR and XFAER:
XBER Bit Mnemonic Name
<20> WDNAK Write Data NO ACK
<18> NRR No Read Response
<17> RSE Read Sequence Error
<16> RER Read Error Response
<15> CNAK Command NO ACK
<13> TTO Transaction Timeout
ADDRESS
Nodespace base address + 0000 002C
3
1
2
8
2
7
2
6
2
5
1
6
1
50
CMD Address Extension Mask
msb−p200−89
MBZ
2–72