VAX 6000 Platform Technical User’s Guide Order Number: EK–600EA–TM-001 This manual serves as a reference for field-level repair or programming for systems based on the VAX 6000 platform. The manual describes the platform architecture, the XMI system bus, the DWMBB XMI-to-VAXBI adapter, and the power and cooling systems found in the H9657-CA/CB/CU cabinet.
First Printing, May 1991 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license.
Contents PREFACE CHAPTER 1 THE VAX 6000 PLATFORM OVERVIEW xiii 1–1 1.1 SPECIFICATIONS 1–2 1.2 SYSTEM FRONT VIEW 1–4 1.3 SYSTEM REAR VIEW 1–5 1.4 CONFIGURATIONS 1–6 1.5 XMI BACKPLANE AND CARD CAGE 1–7 1.6 CONSOLE LOAD DEVICE 1–9 1.7 DWMBB I/O ADAPTER 1–10 1.8 I/O CONNECTIONS 1–11 1.9 POWER SYSTEM 1–12 1.10 COOLING SYSTEM 1–14 1.11 OPTIONS 1–15 CHAPTER 2 THE XMI 2–1 2.1 XMI OVERVIEW 2.1.
Contents 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2–4 2–6 2–7 2–9 2–10 2–11 2–11 2.2 XMI ADDRESSING 2–12 2.2.1 XMI Memory Space 2–13 2–14 2.2.2 XMI I/O Space 2.2.2.1 XMI Private Space • 2–14 2.2.2.2 XMI Nodespace • 2–15 2.2.2.3 I/O Address Space • 2–16 2.2.2.4 VAXBI Adapter I/O Address Space • 2–16 2.2.2.5 How to Find a Register in VAXBI Address Space • 2–17 2.3 ARBITRATION CYCLES 2–20 2.4 XMI CYCLES 2.4.1 Function Codes 2.4.2 Command Cycles 2.4.2.1 Command Field • 2–24 2.4.2.
Contents 2.5.6 2.5.7 2.5.8 2.5.9 2.5.10 2.5.11 Unlock Write Mask Transaction Disown Write Mask Transactions Tag Bad Data Transactions Interrupt and Identify Transactions Implied Vector Interrupt Transactions Transaction Examples 2.5.11.1 Single Quadword Reads • 2–46 2.5.11.2 Multiple Quadword Reads • 2–48 2.5.11.3 Longword and Quadword Writes • 2–50 2.5.11.4 Multiple Quadword Writes • 2–51 2–40 2–41 2–42 2–43 2–45 2–46 2.6 CACHE COHERENCY 2–52 2.7 XMI INITIALIZATION 2.7.
Contents CHAPTER 3 DWMBB ADAPTER 3.1 DWMBB OVERVIEW 3.2 ADDRESS TRANSLATION 3–4 3.2.1 DWMBA Compatibility Mode 3–8 3.2.1.1 DWMBA Compatibility Mode DMA Write Transaction • 3–9 3.2.1.2 DWMBA Compatibility Mode DMA Read Transaction • 3–9 3–10 3.2.2 40-Bit VAX Address Translation 3.2.3 40-Bit Address Translation (4-Kbyte Page Size) 3–11 3–13 3.2.4 40-Bit Address Translation (8-Kbyte Page Size) 3.2.5 DMA Write Transactions—Extended Address Modes 3–15 3.2.
Contents 3.6.4 3.6.5 3.6.6 Full XMI Lockout Mode Programmable Lockout Limit Lockout Deassertion Timer 3–30 3–31 3–32 3.7 COMMANDER ARBITRATION USING RESPONDER REQUEST 3–33 3.8 PROGRAMMABLE TIMEOUTS 3–34 3.9 PROGRAMMABLE VAXBI I/O WINDOW SPACE 3–36 3.10 ECC PROTECTION ON THE PMR DATA PATH 3.10.1 ECC Errors Detected During I/O PMR Read Accesses 3.10.2 ECC Errors Detected During PMR Accesses for DMA Address Translation 3–37 3–38 3.
Contents 3.12.3 3.12.4 3.12.5 3.12.6 3.12.7 3.12.8 3.13 viii Multiple Errors 3–115 Address Translation Mode Errors 3–115 3.12.4.1 Invalid VAXBI Address • 3–116 3.12.4.2 Invalid PFN • 3–116 3.12.4.3 ECC Errors on PMR Data During DMA Address Translation • 3–117 3.12.4.3.1 Uncorrectable ECC Errors • 3–117 3.12.4.3.2 Correctable ECC Errors • 3–117 3.12.4.4 ECC Errors on PMR Data During I/O Reads to PMR • 3–118 3.12.4.4.1 Uncorrectable ECC Errors • 3–118 3.12.4.4.
Contents 3.13.3 3.14 DWMBB/B Module Initialization Sequence DIAGNOSTIC FEATURES 3–133 3.14.1 Internal Loopback Modes 3–134 3.14.1.1 DWMBB/A Module Loopback • 3–134 3.14.1.2 BIIC Loopback • 3–135 3.14.1.3 DMA Loopback • 3–136 3.14.2 DWMBB/A Module Gate Array Transaction Register Files Testing 3–137 3.14.2.1 Executing DMA Writes and Reads in Loopback Mode • 3–141 3.14.2.2 Transaction Register File in Loopback Mode Using DMA Writes and Reads • 3–143 3.14.3 Forcing Bad Parity 3–145 3.14.3.
Contents INDEX FIGURES 1–1 1–2 1–3 1–4 1–5 1–6 1–7 1–8 1–9 1–10 1–11 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 2–21 2–22 2–23 2–24 2–25 2–26 2–27 2–28 2–29 x System Front View System Rear View System Architecture XMI H7242 Inhibit Cable Booting from an Ethernet-Based CD Server DWMBB Adapter Block Diagram Console and Terminal Connectors Power System (Rear View) Airflow Pattern System Options XMI System Block Diagram XMI Node Block Diagram Showing the XMI Co
Contents 2–30 2–31 2–32 2–33 2–34 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 Hexword Data Return with Uncorrectable Read Error Longword and Quadword Writes Octaword Write XMI Initialization Flowchart Failed Hexword Write Transaction DWMBB Adapter Block Diagram VAXBI I/O Address Space for XMI Node 1 DWMBA Compatibility Mode Address 40-Bit Addressing Mode with 512-Byte Page Size 40-Bit Addressing Mode with 4-Kbyte Page Size 40-Bit Addressing Mode with 8-Kbyte Page Size INTR
Contents 2–14 2–15 2–16 2–17 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 3–18 3–19 3–20 3–21 3–22 4–1 4–2 xii I/O Space Transactions Memory Response XMI Registers Abbreviations for Bit Type VAXBI ADDRESS MAPPING VAXBI Commands and Corresponding XMI Transactions XMI Commands and Corresponding VAXBI Transactions DWMBB Interrupt Levels VAXBI Wrapped Read Transactions DWMBB Lockout Limit Lockout Deassertion Timer Values DWMBB Timeout Limit XMI Registers on the DWMBB/A Module X
Preface Intended Audience This manual is for Digital customer service engineers installing and/or repairing a VAX 6000 platform in the field and for OEMs who are writing specialized applications, such as their own operating systems. Document Structure This manual has four chapters. • Chapter 1 gives you a basic introduction to the VAX 6000 platform and its parts. • Chapter 2 tells you about the XMI system bus and its protocol.
Preface Table 1 (Cont.
Preface Table 3 (Cont.
1 The VAX 6000 Platform Overview This chapter provides an overview of the H9657-CA/CB/CU cabinet, the new platform used for VAX 6000 systems. This platform differs from the earlier platform in that the XMI card cage provides +3.3V.
The VAX 6000 Platform Overview 1.1 Specifications The VAX 6000 platform is designed for growth and can be configured for many different applications. Table 1–1 VAX 6000 Platform Differences Item XMI-1 Platform XMI-2 Platform XMI Backplane XMI-1 XMI-2 Cabinet Number 70-24900-XX H9657-CA/CB/CU XTC 20-29176-01 20-29176-02 Power Regulators H7214 (+5V, +5VBB, +13.5V) H7215 (+12V, -12V, -5V, -2V) H7214 (+5V, +13.5V) H7215 (+12V, -12V, -5V, -2V) H7242 (+3.3V, +13.
The VAX 6000 Platform Overview Table 1–2 VAX 6000 Series System Characteristics Physical cm (in) Height 154 (60.5) Width 78 (30.5) Depth 76 (30.0) Weight 341 kg (750 lbs) Environmental Heat dissipation (max) 5440 Btu/hr (5712 KJ/hr) Operating temperature 10o to 40o C (50o to 104o F) Operating humidity 10% to 90% relative humidity Altitude Nonoperational 0 to 9.1 km (8000 to 30,000 ft) Operating 0 to 2.
The VAX 6000 Platform Overview 1.2 System Front View Figure 1–1 System Front View * CONSOLE LOAD DEVICE CONTROL PANEL VAXBI CARD CAGES * XMI POWER REGULATORS VAXBI POWER REGULATORS * XMI CARD CAGE COOLING SYSTEM POWER AND LOGIC BOX TRANSFORMER (50 Hz SYSTEMS ) * OPTIONAL BATTERY BACKUP UNIT DISKS * * msb-0311-90 Components visible from the inside front of the cabinet are shown in Figure 1–1.
The VAX 6000 Platform Overview 1.3 System Rear View Figure 1–2 System Rear View XTC POWER SEQUENCER MODULE XMI POWER REGULATORS XMI CARD CAGE COOLING SYSTEM VAXBI POWER REGULATORS * VAXBI CARD CAGES * ETHERNET AND CONSOLE TERMINAL CONNECTORS POWER AND LOGIC BOX BATTERY BACKUP UNIT * DISKS * AC POWER CONTROLLER * OPTIONAL msb-0312-90 Components visible from the rear of the cabinet are shown in Figure 1–2.
The VAX 6000 Platform Overview 1.4 Configurations The XMI is the 64-bit system bus that interconnects the processors, memory modules, and I/O adapters. A system can be easily upgraded from one model to another. Processor models cannot be mixed in a system. The MS62A and MS65A memories, however, can be used together.
The VAX 6000 Platform Overview 1.5 XMI Backplane and Card Cage The XMI high-speed system bus interconnects processors, memory modules, and I/O adapters. The XMI card cage has 14 slots and a maximum bandwidth of 100 megabytes per second. Figure 1–4 XMI XMI CARD CAGE FRONT Memory Processors XMI CIXCD DEMNA KDM70 msb-0316A-90 The XMI is a limited-length, pended, synchronous bus with centralized arbitration.
The VAX 6000 Platform Overview Each slot of the XMI card cage is hardwired to a 4-bit node ID code that corresponds to the physical slot number in the card cage. The node ID number of the module is its slot position. The nodes are numbered 1 through E (hex) from right to left, as you view the card cage from the front of the cabinet. Figure 1–5 shows a cable used in the H9657 platform that inhibits the +3.3V.
The VAX 6000 Platform Overview 1.6 Console Load Device Several options are available for the console load device. An optional TK tape drive can be installed in the system cabinet or a compact disk server can be used that is accessed over the Ethernet. The InfoServer 100 is an Ethernet-based compact disk (CD) server that is part of a local area network. The CD server is used to access CDROMs for software installation, diagnostics, and on-line documentation.
The VAX 6000 Platform Overview 1.7 DWMBB I/O Adapter The DWMBB adapter provides an information path between the XMI bus and I/O devices on the VAXBI bus. The DWMBB consists of two modules: the DWMBB/A module and the DWMBB/B module. The DWMBB/A module resides on the XMI bus, and the DWMBB/B module resides on the VAXBI bus. Four 30-pin cables, which make up the IBUS, connect the two modules.
The VAX 6000 Platform Overview 1.8 I/O Connections I/O connections are installed on the bulkhead tray and the I/O panel. The I/O tray is located in the rear of the cabinet, between the cooling system and the power regulators, and covers the XMI backplane. The I/O panel is just below the right-hand side of the I/O tray and houses the Ethernet and console terminal ports.
The VAX 6000 Platform Overview 1.9 Power System The power system consists of an H405-E/F AC power controller, the H7206-B power and logic unit, power regulators for the XMI and optional VAXBI, and an H7236-A battery backup unit, also optional. Figure 1–9 Power System (Rear View) H7214, H7215, AND H7242 POWER REGULATORS H7206-B POWER AND LOGIC UNIT H7236-A BATTERY BACKUP UNIT (OPTIONAL) H405-E/F AC POWER CONTROLLER msb-0308-90 Table 1–3 Input Voltage Model No.
The VAX 6000 Platform Overview Table 1–4 DC Power Distribution Voltage Current (Amps) Min. – Max. Description +5V 1 – 130 Main logic supply +3.3V 1 – 80 Main logic supply +12V 0 – 4 Communications devices and TK tape drive –12V 0 – 2.5 Communications devices –5.2V 0 – 20 ECL supply –2V 0 – 7 ECL terminator voltage +5V 1 – 130 Main logic supply +12V 0 – 4 Communications devices –12V 0 – 2.5 Communication devices –5.
The VAX 6000 Platform Overview 1.10 Cooling System The cooling system consists of two blowers, an airflow sensor, a temperature sensor, and an airflow path through the card cages and up to the power regulators. Figure 1–10 Airflow Pattern POWER REGULATORS CARD CAGES BLOWERS FRONT EXTERNAL FRONT VIEW REAR INTERNAL SIDE VIEW msb-0008-89 The cooling system is designed to keep system components at an optimal operating temperature.
The VAX 6000 Platform Overview 1.11 Options System options include the VAXBI card cages and power regulators, battery backup unit, and in-cabinet disks. Figure 1–11 System Options VAXBI POWER REGULATORS VAXBI CARD CAGES BATTERY BACKUP UNIT DISKS msb-0398-90 VAXBI Card Cages and Power Regulators The optional VAXBI I/O interface is a one-channel bus housed in two 6slot VAXBI card cages. Two power regulators supply power to the VAXBI backplane.
2 The XMI This chapter describes the XMI system bus, which includes a backplane and bus interconnect, protocol, and logic.
The XMI 2.1 XMI Overview The XMI is the primary interconnect for the VAX 6000 platform. The XMI supports multiple processors, multiple memory modules, and multiple I/O adapters. Figure 2–1 shows a four-processor system. 2.1.1 XMI System Block Diagram Description Figure 2–1 XMI System Block Diagram CPU 1 CPU 2 CPU 3 CPU 4 +3.
The XMI The XMI consists of the electrical environment of the XMI bus, the protocol observed by a node on the bus, the backplane, and the logic used to implement the protocol. The XMI is a limited length, pended, and synchronous bus with centralized arbitration. Several transactions can be in progress at a given time, allowing highly efficient use of the bus bandwidth. Arbitration and data transfers can occur simultaneously.
The XMI 2.1.2 XMI Corner The XMI uses similar, but incompatible, connector and module technology as the VAXBI bus and, like the VAXBI, XMI modules have an area with predefined etch with custom components, which serves as the interface between the module and the XMI bus. This predefined etch and components is called the XMI Corner.
The XMI The custom components in the XMI Corner are called XLATCH and XCLOCK. Both components are implemented in CMOS and interface node-specific logic to the XMI Corner components over the XMI Corner interface (XCI) bus. The XMI Corner, in turn, interfaces directly to the XMI bus. (See Figure 2–2.) Each node has a set of three clock signals, which are distributed radially to each node from a central source on the backplane.
The XMI 2.1.3 XMI Data Transactions The XMI supports various data transactions, as shown in Table 2–2.
The XMI 2.1.4 XMI Terms The following terms are used to describe XMI transactions: Term Definition Node A hardware device that connects to the XMI backplane. Transfer The smallest quantum of work that occurs on the XMI. An example of a transfer is the command cycle of a read. Another example is the command cycle for a write, followed by data cycles. Cycle The complete execution of one XMI clock time period. Transaction The logical task being performed (such as a read).
The XMI Term Definition Longword A single 32-bit entity. 63 32 31 longword 1 0 longword 0 msb−p158−89 Quadword A single 64-bit entity. 63 0 quadword msb−p159−89 Octaword A single 128-bit entity (two quadwords). 127 64 / / quadword / / 63 0 / / quadword / / msb−p160−89 Hexword A single 256-bit entity (four quadwords). 255 192 / / quadword / / 191 128 / / quadword / / 127 64 / / quadword / / 0 63 / / quadword / / msb−p161−89 Block 2–8 A hexword.
The XMI 2.1.5 Wraparound Reads Read data is returned in a specific pattern referred to as "wraparound read" for octaword or hexword read operations. In a wraparound read, the specifically addressed quadword is returned first, independent of alignment. The remaining data in the naturally aligned block of data containing the addressed quadword is returned in subsequent transfers. A naturally aligned octaword is pointed to by an address that ends in 0, 10, 20, 30, and so forth.
The XMI 2.1.6 XMI Interrupt Transactions The XMI supports three types of interrupt transactions, listed in Table 2–3. Table 2–3 XMI Interrupt Transactions Type Mnemonic Interrupt Request INTR Identify (Interrupt Acknowledge) IDENT Implied Vector Interrupt IVINTR The INTR and IDENT transactions implement device interrupts. An I/O node issues an INTR transaction to a processor to interrupt the processor at a specified interrupt priority level (IPL).
The XMI 2.1.7 Arbitration The XMI protocol includes arbitration because, at any time, any or all of the nodes may desire the use of the XMI. Arbitration determines which node gains the XMI when more than one node requests the XMI simultaneously. Table 2–4 XMI Arbitration Lines Name Use XMI CMD REQ L Initiates XMI transactions XMI RES REQ L Returns data XMI GRANT L Indicates which node has been granted the XMI bus for the next cycle The VAX 6000 platform supports an XMI bus of 14 nodes.
The XMI 2.2 XMI Addressing The XMI supports one terabyte (240 bytes) of address space. The VAX 6000 series systems use a maximum of (232 bytes). These systems use one of three addressing modes: • 30-bit mode used by VAX 6000 Models 200 through 500 • 32-bit mode used by VAX 6000 models above 500 • 30-bit mode in a 32-bit environment used by VAX 6000 models above 500 Figure 2–3 shows how memory and I/O space are divided in the 30-bit and the 32-bit modes.
The XMI 2.2.1 XMI Memory Space Memory address space is the lower part of the address space no matter which address mode, 30-bit or 32-bit, is used. The maximum amount of I/O space available is 512 Mbytes in either mode. Selection of memory space for a system using a 30-bit address space is dependent upon the state of bit <29>, the most significant bit in the 30-bit address. If bit <29> is clear, memory is addressed. If bit <29> is set, I/O space is addressed.
The XMI 2.2.2 XMI I/O Space XMI I/O space is divided into private space, nodespace, and ten I/O adapter address space regions.
The XMI 2.2.2.2 XMI Nodespace The VAX 6000 platform XMI nodespace is a collection of 16 512-Kbyte regions located from E180 0000 to E1FF FFFF (32-bit address) or from 2180 0000 to 21FF FFFF (30-bit address). Nodes 0 and F are not implemented. Each XMI node is allocated one of the 512-Kbyte regions for its control and status registers.
The XMI 2.2.2.3 I/O Address Space I/O adapter address space consists of ten 32-Mbyte address regions used to access I/O adapters. See documentation for each XMI adapter to determine how each implements access through I/O space addressing. The special case of the XMI-to-VAXBI adapter addresssing is covered in Section 2.2.2.4. 2.2.2.4 VAXBI Adapter I/O Address Space Longword-length references directed to a VAXBI’s I/O adapter address space will be reissued on that VAXBI bus.
The XMI 2.2.2.5 How to Find a Register in VAXBI Address Space The first part of a VAXBI adapter’s physical XMI address depends on which XMI slot the DWMBB/A module occupies. The second part of the address depends on the adapter’s VAXBI node number, which is shown in the SHOW CONFIGURATION display. NOTE: VAXBI slot and node numbers are not identical.
The XMI To get the address for the DMB32 Device Register (DTYPE), do the following: 1 From Table 2–5 find XMI node E and take the 2-digit prefix for the start of that node’s window space (FC or 3C depending upon address mode). 2 From Table 2–7 find VAXBI node 4 and in column 2 you can see that the starting address for VAXBI node 4 is xx00 8000. 3 Combine this second number with the 2-digit prefix. You now have the adapter’s base address (FC00 8000) in VAXBI address space, indicated by lowercase bb.
The XMI Table 2–8 VAXBI Registers Name Mnemonic Address1 Device Register DTYPE bb+00 VAXBI Control and Status Register VAXBICSR bb+04 Bus Error Register BER bb+08 Error Interrupt Control Register EINTRSCR bb+0C Interrupt Destination Register INTRDES bb+10 IPINTR Mask Register IPINTRMSK bb+14 Force-Bit IPINTR/STOP Destination Register FIPSDES bb+18 IPINTR Source Register IPINTRSRC bb+1C Starting Address Register SADR bb+20 Ending Address Register EADR bb+24 BCI Control and S
The XMI 2.3 Arbitration Cycles The XMI protocol includes arbitration because, at any time, any or all of the nodes may desire the use of the XMI. Arbitration determines which node gains the XMI when more than one node requests the XMI simultaneously. Arbitration cycles occur in parallel with data transfer cycles, since the XMI has a set of arbitration-dedicated lines. Figure 2–6 XMI Arbitration Block Diagram XMI HOLD L XMI SUP L XMI CMD REQ[1] L XMI RES REQ[1] L Node #1 XMI GRANT[1] L . . . . . . . .
The XMI The XMI protocol architecturally supports up to 16 XMI nodes. However, the VAX 6000 implementation supports 14 nodes. Each node on the XMI bus has a hexadecimal identification number (1 through E) called the node ID, which is provided by the node’s hardwired XMI NODE ID<3:0> H lines. The physical slot number equals the node ID. Slot 1 is the rightmost slot in the XMI card cage when viewed from the front of the cabinet. Any or all nodes may desire the use of the XMI at any given time.
The XMI 2.4 XMI Cycles The purpose of an XMI cycle is determined by four signal lines on the XMI backplane, XMI F<3:0> L. 2.4.1 Function Codes The XMI uses four lines to encode the function being performed on the bus. Table 2–9 lists the function codes.
The XMI 2.4.2 Command Cycles During XMI command cycles, commander nodes initiate XMI transactions. The commander drives its commander ID on XMI ID<5:0> L and drives command information on D<63:0> L, as shown in Figure 2–7 and Figure 2–8.
The XMI 2.4.2.1 Command Field The Command field is XMI D<63:60> L. The Command field specifies the transaction being initiated in the command cycle. (See Table 2–10.
The XMI 2.4.2.2 Mask Field The Mask field is XMI D<47:32> L. The Mask field supplies byte-level mask information for the XMI Write Mask and Unlock Write Mask transactions. During nonwrite transactions this field is a "don’t care," but proper parity is still generated. (See Figure 2–9.) The maximum length of a write transaction other than a Disown Write is one octaword. Disown Writes are always hexword writes. Octaword writes require 16 mask bits in the upper longword of the command.
The XMI 2.4.2.3 Length Field The Length field is XMI D<31:30> L. The Length field is used to define the number of words in the XMI data transfer. Table 2–11 shows the Length field coding. Longword-length transactions are only used in I/O space. Quadword-, octaword-, and hexword-length transactions are only used in memory space. Hexword lengths are used for Read, Write, Ownership Read, Disown Write Mask, Tag Bad Data, and Interlock Read transactions. Table 2–11 XMI Transaction Length Codes 2.4.2.
The XMI Figure 2–10 XMI Address Interpretation A, i= 4 3 2 1 0 Read longword s s s s s Read quadword s s x x x Read octaword s s x x x Read hexword s s x x x Write longword s s s s s Write quadword s s x x x Write octaword s x x x x Write hexword x x x x x s = significant x = don’t care msb−p173−89 The relationship between the high and low words, the state of A<1>, and the data bits is: A<1> = XMI D<1> = 1 A<1> = XMI D<1> = 0 ) ) high word ) D<31:16> low word ) D<15:0> The data retu
The XMI 2.4.2.6 Node Specifier Field The Node Specifier field is XMI D<15:0> L. During command cycle interrupt transactions (INTR, IDENT, IVINTR), the Node Specifier field is used to specify the source or destination of an interrupt. (See Figure 2–8.) The relationship between bits in the Node Specifier field and the source or destination of an interrupt transaction is shown in Figure 2–11. The VAX 6000 uses nodes 1 through E.
The XMI 2.4.3 Write Data Cycles A function code of 0010 identifies an XMI write data cycle. Write data cycles immediately follow the XMI command cycle during an XMI write transfer. During this cycle, the commander drives its ID on XMI ID<5:0> L and drives write data on D<63:0> L. The full 64 bits of data are used during quadword-length or larger writes. For longword-length writes, only the lower longword D<31:0> L is used and the value of the upper longword is unspecified.
The XMI 2.4.5 Locked Response Cycle (LOC) The Locked Response indicates that the location specified in an Interlock Read or Ownership Read transaction is not accessible at this time. Such a location is either owned by another node or involved in an interlock pair of transactions. Therefore, the LOC response is given by memory for one of the following reasons: • The command is an IREAD and the location is currently locked by another node.
The XMI 2.5 XMI Transactions XMI transactions are listed in Table 2–12. Table 2–13 and Table 2–14 summarize XMI transaction behavior.
The XMI Table 2–13 Memory Space Transactions Command Length Used By Command Cycle Acknowledgments Request Type Flow Control Possible Responses 1 Cdr SUP GRDx, CRDx,2 RER3 READ HW, OW, QW CPU, I/O ACK or NO ACK IREAD QW I/O4 ACK or NO ACK1 Cdr SUP GRDx, CRDx,2 LOC,1 RER3 OREAD HW CPU ACK or NO ACK1 Cdr SUP GRDx, CRDx,2 LOC,1 RER3 WMASK HW, OW, QW CPU, I/O4 ACK or NO ACK1 Cdr SUP UWMASK HW, OW, QW CPU, I/O4 ACK or NO ACK1 Cdr SUP DWMASK HW CPU ACK or NO ACK1 Cdr,
The XMI 2.5.1 Memory Block State A memory block (a hexword) can be in one of the following states at any given time: 1 Free, indicating that the memory block is neither OWNED nor INTERLOCKED. 2 Interlocked, indicating that the memory block is INTERLOCKED as a result of a successful IREAD transaction. 3 Owned, indicating that the memory block is OWNED by a writeback cache within the system as a result of a successful OREAD transaction.
The XMI 2.5.2 Read Transaction Read (READ) transactions (see Figure 2–12) are used to transfer a longword, quadword, octaword, or hexword of data from the responder to the commander. The data is naturally aligned and delivered in wraparound order. Wraparound reads are described in Section 2.1.5. A Read transaction is initiated by a commander driving the XMI address and function lines to represent a longword read, quadword read, octaword read, or hexword read.
The XMI 2.5.3 Interlock Read Transaction An Interlock Read (IREAD) transaction (see Figure 2–13), combined with a corresponding Unlock Write Mask transaction, permits mutually exclusive access to memory space locations. The effect of an IREAD transaction depends on the state of the interlock bit and the ownership bit in memory.
The XMI Locks are supported for all XMI memory space locations and are implementation dependent for XMI I/O space. The minimum memory space interlock granularity is a hexword (see Figure 2–14). There are no multiple interlocks within a single naturally aligned hexword. Noninterlock reads (except OREADs) are not affected by the state of the lock, and they read the specified locations even if the lock is set.
The XMI 2.5.4 Ownership Read Transaction The Ownership Read (OREAD) transaction (see Figure 2–15) is used with the Disown Write Mask transaction for the block ownership writeback protocol.
The XMI 2.5.5 Write Mask Transaction Write Mask (WMASK) transactions (see Figure 2–16) transfer data from the commander to the responder. Figure 2–16 Write Mask Command 6 3 0111 6 5 5 5 0 9 8 7 MBX 4 4 8 7 3 3 3 2 2 1 0 9 WRITE MASK ADDRESS<39:30> WRITE MASK COMMAND 0 ADDRESS<29:0> LENGTH 00 01 10 11 = = = = Hexword Longword Quadword Octaword msb−p189−89 WMASK transactions transfer a pattern of bytes that fit into a longword, quadword, octaword, or hexword from the commander to the responder.
The XMI the bit is one, then that byte is written. For hexword-length Write Mask transactions, the responder ignores the mask and writes all 32 bytes, unless there is a matching entry in the deferred queue. Then only bytes that were not updated by the deferred write are updated. The MS65A memory module is quadword organized, and therefore all writes that write less than an aligned quadword for each write data cycle result in the generation of a read/modify/write operation in the memory.
The XMI 2.5.6 Unlock Write Mask Transaction The Unlock Write Mask (UWMASK) transaction (see Figure 2–17), combined with a corresponding Interlock Read transaction, is used to relinquish the locked memory location after an Interlock Read.
The XMI 2.5.7 Disown Write Mask Transactions The Disown Write Mask (DWMASK) transaction (see Figure 2–18) is used with the Ownership Read transaction to implement the block ownership writeback protocol. The OREAD and DWMASK commands are used by the CPU nodes that contain writeback caches.
The XMI 2.5.8 Tag Bad Data Transactions The Tag Bad Data (TBDATA) transaction (see Figure 2–19) is a write used in place of a DWMASK transaction to mark bad a cache location that has supplied corrupted data. Since the XMI processors support ECC for cache data transfers, it takes a double-bit error to require the use of a TBDATA transaction. System software associates the bad data with an actual process by marking the corrupt location as bad, since the first read reference to this location will fail.
The XMI 2.5.9 Interrupt and Identify Transactions Any I/O device can send an interrupt to one or more processor nodes. A processor eventually issues an IDENT and then performs the necessary service routine. Each processor on the XMI has the capability of handling 64 interrupts, one interrupt for each of the four interrupt priority levels (IPLs) for each of the 16 possible XMI nodes.
The XMI Figure 2–21 Identify Command 6 3 1001 6 5 0 9 4 4 8 7 Reserved 3 3 2 1 2 1 1 1 1 1 0 9 8 7 6 5 Don’t Care IDENT COMMAND 0 NODE ID IPL 14 IPL 15 IPL 16 1PL 17 INTERRUPT SOURCE msb−p194−89 Figure 2–22 Identify Response 6 3 1 1 6 5 Reserved 2 1 0 VECTOR MBZ msb−p195−89 2–44
The XMI 2.5.10 Implied Vector Interrupt Transactions The Implied Vector Interrupt (IVINTR) is a single-cycle transfer used to implement VAX interprocessor interrupts and write error interrupts where the interrupt priority and interrupt vector are implied by the type of interrupt (see Figure 2–23).
The XMI 2.5.11 Transaction Examples Examples are found in the following subsections: 2.5.11.
The XMI The Read transactions consist of a command transfer followed by a return data transfer, as shown in Figure 2–24. The two transfers are the command (FUNCT = CMD) and the read data response (FUNCT = GRD0). The commander arbitrates for the bus in cycle 0 and wins. In cycle 1, it drives the function, command, address of the read, and its own ID (for later use to identify the returning data). In cycle 3, the responder confirms receipt of the information.
The XMI 2.5.11.
The XMI The four multiple quadword Read transactions move either 16 bytes (octaword) or 32 bytes (hexword) of data from the responder to the commander. Figure 2–26 is the command transfer of the transaction. The Interlock Read checks the state of the ownership and lock bits in the memory and qualifies the request, based on their state. This illustration applies to both octaword and hexword reads. Figure 2–27 is a diagram of the return data transfer applicable to octaword reads.
The XMI Figure 2–30 Hexword Data Return with Uncorrectable Read Error 0 FUNCT DATA ID CONF ARB 1 2 3 4 |GRD0|GRD1|RER | | |DAT0|DAT1| | | |CMDR|CMDR|CMDR| | | | |ACK |ACK | |RESP|HOLD|HOLD| | 5 | | | |ACK | | | | | | msb−p182−89 2.5.11.3 Longword and Quadword Writes Longword and quadword writes can be either Write Mask or Unlock Write Mask transactions. Longword and quadword writes move the number of bytes specified by the Mask field.
The XMI 2.5.11.4 Multiple Quadword Writes The multiple quadword writes are octaword Write Mask, octaword Unlock Write Mask, hexword Write Mask, and hexword Unlock Write Mask transactions. Multiple quadword writes identify the first cycle of the transfer with the desired write length. HOLD is asserted while successive cyles provide new data so that there are no null cycles in between.
The XMI 2.6 Cache Coherency All cache-resident nodes monitor bus traffic to remain consistent. XMI processors never generate memory references between an Interlock Read and the corresponding Unlock Write. Caches are high-speed local memory subsystems residing between the processor and main memory. Cache control logic maintains the local copies of data likely to be used by the processor.
The XMI 2.7 XMI Initialization Regardless of the method used to cause a node to initialize, the initialization process consists of the same steps.
The XMI 2.7.1 Causes of an Initialization Three causes of XMI initialization are: 2.7.2 • Power-down/power-up • System reset • Node reset Power-Up On power-up, the XMI AC LO L, XMI DC LO L, and XMI RESET L lines are sequenced to provide initialization of all nodes in the system. The XMI initialization flowchart is shown in Figure 2–33. During normal power-up, a node cannot access XMI-accessible memory space locations until the deassertion of XMI AC LO L.
The XMI 2.7.3 System Reset A power-down/power-up sequence can be emulated through the use of the XMI RESET L line, which causes the sequencing of XMI AC LO L and XMI DC LO L in the same way as a true power-down/power-up sequence. This allows all nodes in the system to be returned (or "reset") to their power-up state without cycling the power supplies. The XTC power sequencer is used to carry out the reset sequence.
The XMI 2.8 XMI REGISTERS This section describes the registers required for various types of nodes. Each XMI node is required to have a set of registers in a specified location within the node’s nodespace, as shown in Table 2–16. Table 2–17 defines the abbreviations used to describe the type of bits in the register descriptions.
XMI Registers Device Register (XDEV) Device Register (XDEV) The Device Register contains information to identify the node. Both fields are loaded during node initialization. A zero value indicates an uninitialized node.
XMI Registers Bus Error Register (XBER) Bus Error Register (XBER) The Bus Error Register contains error status on a failed XMI transaction. This status includes the commander ID, and an error bit that indicates the type of error that occurred. This status remains locked up until software resets the error bit(s).
XMI Registers Bus Error Register (XBER) bit<31> Name: Error Summary Mnemonic: ES Type: RO, 0 ES represents the logical OR of the error bits in this register. Therefore, ES asserts when one or more of the following error bits assert.
XMI Registers Bus Error Register (XBER) bit<29> Name: Node Halt Mnemonic: NHALT Type: R/W, 0 Writing a one to NHALT forces the node to go into a "quiet" state while retaining as much state as possible. The CPU halts and goes into console mode waiting for console commands. bit<28> Name: XMI BAD Mnemonic: XBAD Type: R/W, 1 On reads, XBAD indicates the state of the XMI BAD signal. A one indicates that BAD is asserted.
XMI Registers Bus Error Register (XBER) bit<24> Name: Inconsistent Parity Error Mnemonic: IPE Type: R/W1C, 0 When set, IPE indicates that the node has detected a parity error on an XMI cycle and the confirmation for the errored cycle was ACK. This indicates that at least one node (the responder) detected good parity during the cycle time that this node detected a parity error. Only XMI processor nodes are required to implement this bit. If not implemented, nodes return zero.
XMI Registers Bus Error Register (XBER) bit<20> Name: Write Data NO ACK Mnemonic: WDNAK Type: R/W1C, 0 When set, WDNAK indicates that a Write data cycle (GRDn, CRDn, LOC, RER) transmitted by the node has received a NO ACK confirmation. bit<19> Name: Corrected Read Data Mnemonic: CRD Type: R/W1C, 0 When set, CRD indicates that the node has received a CRDn read response. Only XMI commander nodes are required to implement this bit. If not implemented, nodes return zero.
XMI Registers Bus Error Register (XBER) bit<15> Name: Command NO ACK Mnemonic: CNAK Type: R/W1C, 0 When set, CNAK indicates that a command cycle transmitted by the node has received a NO ACK confirmation caused by either a reference to a nonexistent memory location or a command cycle parity error. Only XMI commander nodes are required to implement this bit. If not implemented, nodes return zero. For commanders implementing error recovery, this bit is set only if the reattempts fail.
XMI Registers Bus Error Register (XBER) bit<10> Name: Selt-Test Fail Mnemonic: STF Type: R/W1C, 1 When set, STF indicates that the node has not yet passed its self-test. This bit is cleared by the user interface when the node passes its self-test. bits<9:4> Name: Failing Commander ID Mnemonic: FCID Type: RO This field logs the commander ID of a failing transaction. Only XMI commander nodes are required to implement this field. If not implemented, nodes return zero.
XMI Registers Bus Error Register (XBER) bit<3> Name: Enable Hexword Write Mnemonic: EHWW Type: RO, 0 EHWW is used to enable/disable the transmission of hexword writes of all types (Write Mask, Unlock Write Mask, Disown Write Mask) on those controllers that implement them. When EHWW is set, the commander is permitted to generate hexword writes; when EHWW is clear, the commander is restricted from generating hexword writes. Commanders that do not implement hexword writes have EHWW as zero.
XMI Registers Failing Address Register (XFADR) Failing Address Register (XFADR) The Failing Address Register logs address and length information associated with a failing transaction. Only XMI commander nodes are required to implement this register. XFADR is the lower 32 bits of a 64-bit register formed by concatenating XFADR and XFAER. The 64-bit register is used to log command, address, length, and write mask information (in the case of write transactions) associated with a failing transaction.
XMI Registers Failing Address Register (XFADR) bits<31:30> Name: Failing Length Mnemonic: FLN Type: RO FLN logs the value of XMI D<31:30> during the command cycle of a failing transaction and indicates the length of the transaction. bits<29:0> Name: Failing Address Mnemonic: None Type: RO The Failing Address field logs the value of XMI D<29:0> during the command cycle of a failing transaction. In 30-bit mode the XFADR contains the entire address.
XMI Registers XMI General Purpose Register (XGPR) XMI General Purpose Register (XGPR) The XGPR is a general purpose register that is visible to the XMI bus. This register is used during self-test and by the ROM-based diagnostics. ADDRESS Nodespace base address + 0000 000C 3 1 0 XMI General Purpose Register (XGPR) msb−p201−89 bits<31:0> Name: XMI General Purpose Register Mnemonic: XGPR Type: R/W, 0 The general purpose register is used by self-test and during ROMbased diagnostics.
XMI Registers Node-Specific Control and Status Register (NSCSR) Node-Specific Control and Status Register (NSCSR) This optional register is node-specific. ADDRESS Nodespace base address + 0000 001C 3 1 0 Node−Specific Control and Status Register (NSCSR) msb−p202−89 bits<31:0> Name: Reserved Mnemonic: None Type: Varies Reserved for node-specific use. See the appropriate chapter for each module that implements NSCSR.
XMI Registers XMI Control Register (XCR) XMI Control Register (XCR) The XMI Control Register contains toggles for various XMI and node-specific functions.
XMI Registers XMI Control Register (XCR) bit<5> Name: Corrected Read Data Interrupt Disable Mnemonic: CRDID Type: RO, 0 CRDID controls the generation of interrupts caused by corrected read data. A zero enables interrupts; a one disables interrupts. ) bits<4:3> Name: Trigger Control Mnemonic: TRIGC Type: RO, 0 TRIGC controls the setting of the XMI TRIGGER L signal. The default code of zero means that the signal is never asserted. The codes of one, two, or three are undefined.
XMI Registers Failing Address Extension Register (XFAER) Failing Address Extension Register (XFAER) The Failing Address Extension Register logs command, address, and write mask information (in the case of write transactions) associated with a failing transaction. Only XMI commander nodes are required to implement this register. XFAER is the higher 32 bits of a 64-bit register formed by concatenating XFADR and XFAER.
XMI Registers Failing Address Extension Register (XFAER) bits<31:28> Name: Command Mnemonic: CMD Type: RO CMD logs the value of XMI D<63:60> during the command cycle of a failing transaction. The field contains the command code of the transactions during the command cycle. bits<27:26> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero.
XMI Registers Bus Error Extension Register (XBEER) Bus Error Extension Register (XBEER) XBEER is used to capture various XMI node errors. ADDRESS Nodespace base address + 0000 0034 3 1 8 7 Node−specific error bits 3 2 1 0 MBZ Unexpected Read Response (URR) Only LOC Response (OLR) Second Error Occurred (SEO) msb−p204−89 bits<31:8> Name: Reserved Mnemonic: None Type: RO, 0 Reserved for node-specific error bits or RO or R/W1C control bits.
XMI Registers Bus Error Extension Register (XBEER) bit<1> Name: Only LOC Response Mnemonic: OLR Type: R/W1C, 0 OLR indicates, when set, that the node received only LOC responses when it tried or retried the read-type transaction. bit<0> Name: Second Error Occurred Mnemonic: SEO Type: R/W1C, 0 SEO indicates, when set, that a second hard error occurred while XBER was reporting a hard error. While SEO is set, the bits reporting the first error are not changed.
The XMI 2.9 XMI Errors The XMI bus detects all single-bit transmission-related errors on XMI D<63:0> L, XMI F<3:0> L, XMI ID<5:0> L, XMI P<2:0> L, and XMI CNF lines. The XMI protocol permits XMI commanders to recover from all transient memory space read/write transaction errors as well as from most I/O space read/write transaction errors. 2.9.1 Error Conditions 2.9.1.1 Parity Error To detect single-bit errors, all nodes monitor parity of the bus.
The XMI 2.9.1.3 2.9.1.4 Transaction Timeout The XMI protocol specifies that a timeout of 16 milliseconds be used by commanders to detect transaction failure. Responders ensure that transactions do not exceed these timeout values. • Response Timeout—An XMI Read, Interlock Read, or IDENT transaction is considered to have failed if a commander does not receive all read responses before the timeout cycle value expires.
The XMI Figure 2–34 Failed Hexword Write Transaction Missing First Data Cycle −−−−−−−−−−−−−−−−−−−−−−−− FUNCT DATA CONF |CMD |XXXX|WDAT| WDAT | WDAT | WDAT | | |WRTM|XXXX|DATA| DATA | DATA | DATA | | | | |ACK |NO ACK|NO ACK|NO ACK|NO ACK| Missing Second Data Cycle −−−−−−−−−−−−−−−−−−−−−−−−− FUNCT DATA CONF |CMD |WDAT|XXXX|WDAT| WDAT | WDAT | | |WRTM|DATA|XXXX|DATA| DATA | DATA | | | | |ACK |ACK |NO ACK|NO ACK|NO ACK| msb−p213−89 2.9.
The XMI 2.9.3 Error Recovery Error recovery involves one or more reattempts of the failed transaction before reporting a hard error. A failed XMI transaction is retried under the following circumstances: 2.9.4 • All transactions receiving a NO ACK confirmation for the command cycle are retried automatically by the hardware. The NO ACK can result from either a reference to nonexistent memory locations (NXM) or from bus parity errors. Transactions failing the retry are assumed to be to an NXM.
The XMI • The DWMBB being unable to complete a VAXBI-to-XMI windowed write operation. Then the DWMBB issues a write error IVINTR transaction to the nodes designated in the DWMBB AIVINTR destination register. This results in system software failure. Processor nodes also use the memory error interrupt (IPL 1D (hex)) to report other node-specific error conditions, such as potential cache coherency problems or write buffer errors.
3 DWMBB Adapter The DWMBB XMI-to-VAXBI adapter provides an information path between the XMI bus and I/O devices on the VAXBI bus.
DWMBB Adapter 3.1 DWMBB Overview The DWMBB XMI-to-VAXBI adapter provides an information path between the XMI bus and I/O devices on the VAXBI bus. The DWMBB consists of two modules: the DWMBB/A XMI module and the DWMBB/B VAXBI module. The IBUS connects the two modules. Figure 3–1 shows the DWMBB block diagram.
DWMBB Adapter The DWMBB/A module contains an XMI Corner, register files, XMI required registers, DWMBB/A module-specific registers, page map registers, and control sequencers for the XMI interface. The DWMBB/B module contains a VAXBI Corner, interconnect drivers, control sequencers to handle the control of the data transfer, status bits to/from the DWMBB/A module’s register files and the BIIC, DWMBB/B module-specific registers, decode logic for DMA operations, and VAXBI clock-generation circuitry.
DWMBB Adapter 3.2 Address Translation The DWMBB is an XMI-to-VAXBI adapter for systems that support 30 bits or more of address space. Figure 3–2 shows the VAXBI I/O address space for XMI node 1. Figure 3–2 VAXBI I/O Address Space for XMI Node 1 XMI NODE 1 32−bit Addr. VAXBI Address (hex) E200 0000 2000 0000 VAXBI I/O Address Space Device 8 Kbytes E200 2000 2000 2000 Device 1 8 Kbytes E200 4000 2000 4000 Device 2 8 Kbytes VAXBI Device Registers 128 Kbytes .
DWMBB Adapter DWMBB address translation uses a mapping register scheme. The page map registers (PMRs) are implemented in RAM and provide 64 K (65,536) 32-bit locations. All mapping register locations are maintained by system software, which ensures that all required page frame numbers (PFNs) loaded in the mapping registers are valid before any I/O device initiates a DMA transaction.
DWMBB Adapter Table 3–2 VAXBI Commands and Corresponding XMI Transactions VAXBI Command XMI Transaction Read (READ) Read Longword Quadword (DWMBB returns requested longword to the VAXBI) Quadword Quadword Octaword Octaword Interlock Read with Cache Intent (IRCI) Interlock Read Longword Quadword (DWMBB returns requested longword to the VAXBI) Quadword Quadword Octaword Octaword Read with Cache Intent (RCI) Read Longword Quadword (DWMBB returns requested longword to the VAXBI) Quadword
DWMBB Adapter Table 3–2 (Cont.) VAXBI Commands and Corresponding XMI Transactions VAXBI Command XMI Transaction Broadcast (BDCST) Not supported (NO ACK to VAXBI) Interprocessor Interrupt (IPINTR) Interrupt at IPL 161 STOP Not supported (NO ACK to VAXBI) 1 The DWMBB responds to VAXBI IDENTs that are directed to it under three different conditions. All three conditions are implemented within the DWMBB/B module’s BIIC. These conditions are as follows: 1.
DWMBB Adapter 3.2.1 DWMBA Compatibility Mode There are two different XMI-to-VAXBI adapters, the DWMBA and the DWMBB. The basic difference is that the DWMBB has a more extensive address space. The DWMBA compatibility mode is the default mode for the DWMBB after power-up and XMI node reset. While in this mode the DWMBB does not perform address translation. This mode requires that the value loaded into the BIIC’s Starting Address Register be less than the value of its Ending Address Register.
DWMBB Adapter 3.2.1.1 DWMBA Compatibility Mode DMA Write Transaction All DMA writes from the VAXBI are performed as disconnected writes. Therefore, the VAXBI is released once the DMA command/address (C/A) and write data to the DWMBB is ACKed, even though the DWMBB has not completed the transaction on the XMI. The execution of a DMA write transaction starts when the DWMBB/B module detects a DMA write directed to memory space.
DWMBB Adapter 3.2.2 40-Bit VAX Address Translation The 40-bit VAX address translation mode is enabled by setting the Map Register Enable field in the DWMBB/A Utility Register (AUTLR) bits <19:18> to one. When in this mode the DWMBB translates the address of any DMA transaction received from the VAXBI into a 40-bit XMI address. Although the full 40 bits are not used, the lower 32 are used in VAX 6000 models above 500.
DWMBB Adapter Figure 3–4 40-Bit Addressing Mode with 512-Byte Page Size 3 3 2 2 1 0 9 8 VAXBI A<31:0> 2 2 5 4 0 LEN 0 9 8 PMR INDEX ADDRESS 0 PAGE OFFSET Access PMR for PMRE 3 3 2 1 0 9 PMRE 0 PFN V 0 Check if PFN is valid 3 3 9 8 XMI A<39:0> 0 9 8 0 XMI PHYSICAL ADDRESS Bit <39> (the I/O select) is always forced to 0 msb−p085−89 3.2.
DWMBB Adapter The steps used for the 40-bit address translation using the 4-Kbyte page sizes are as follows: 1 Check the upper address bits: VAXBI A<29:28> must be zero. 2 Access PMR for PMRE: VAXBI A<27:12> is an index into the PMR to fetch the PMRE. 3 Check PMRE valid bit: If PMRE<31> = 1, then PFN is valid; otherwise PFN is invalid and the transaction is aborted. 4 ECC check: If no uncorrectable error, then PFN is good; otherwise PFN is bad and the transaction is aborted.
DWMBB Adapter 3.2.4 40-Bit Address Translation (8-Kbyte Page Size) When 40-bit address translation mode with 8-Kbyte page sizes is enabled, the DWMBB translates the address of any DMA transaction received into a 40-bit XMI address. All 512 Mbytes of VAXBI memory address space are mapped, because the 64 K entries are sufficient to map the 512 Mbytes with 8-Kbyte pages. In this mode the value loaded into the BIIC’s Starting Address Register must be less than the value of the Ending Address Register.
DWMBB Adapter Figure 3–6 40-Bit Addressing Mode with 8-Kbyte Page Size 3 3 2 2 1 0 9 8 VAXBI A<31:0> LEN 0 1 1 3 2 0 PMR INDEX ADDRESS PAGE OFFSET Access PMR for PMRE 3 3 2 1 0 9 PMRE 2 2 6 5 0 PFN V 0 Unused Check if PFN is valid 3 3 9 8 XMI A<39:0> 0 1 1 3 2 0 XMI PHYSICAL ADDRESS Bit <39> (the I/O select) is always forced to 0 msb−p087−89 3–14
DWMBB Adapter 3.2.5 DMA Write Transactions—Extended Address Modes All DMA writes from the VAXBI are performed as disconnected writes. Therefore, the VAXBI is released once the DMA command/address (C/A) and write data to the DWMBB have been transferred, even though the DWMBB has not completed the transaction on the XMI. The execution of a DMA write transaction starts when the DWMBB/B module detects a DMA write directed to memory space.
DWMBB Adapter 3.3 I/O Transactions I/O transactions originate from a processor on the XMI and are independent of the address translation mode. The DWMBB uses two regions of I/O address space: XMI nodespace and VAXBI nodespace. The XMI nodespace, assuming a 32-bit XMI address, has the range (all in hex) of E180 0000 + (8 0000 * XMI Node ID) through E184 01FC + (8 0000 * XMI Node ID). Not all addresses in this range are used.
DWMBB Adapter 3.3.2 I/O References to the PMRs An I/O read transaction directed to a page map register (PMR) is first latched into the DWMBB/A module. Parity is checked and, if no errors are detected and no DMA transaction is in progress, the specific PMR is accessed. If a DMA transaction is in progress, the PMR read is not done until the DMA transaction completes its PMR access.
DWMBB Adapter 3.4 Interrupts Interrupt commands are issued by the DWMBB at IPL 17 (hex) through IPL 14 (hex) to one or more XMI commanders. The commander(s) designated to receive the interrupt are flagged by the destination mask in XMI D<15:0>.
DWMBB Adapter Both modules of the DWMBB detect conditions that require an interrupt to be issued, but only the DWMBB/B module issues interrupts. If the DWMBB/A module detects an interrupt condition, it flags the DWMBB/B module using an IBUS signal. The DWMBB/B module then issues the interrupt when it detects this flag. The XMI commander eventually responds to the INTR command by issuing an IDENT command to the DWMBB at the same IPL.
DWMBB Adapter Table 3–4 DWMBB Interrupt Levels 3–20 IPL Name Vector Offset Source 17 DWMBB-Detected Error Interrupt XMI 7 BVR 17 DWMBB BIIC Level 7 Interrupt, VAXBI<13:9> equal to 0 VAXBI 7 BVOR 17 DWMBB BIIC Offsettable Level 7 Interrupt, VAXBI<13:9> not equal to 0 VAXBI 7 None 17 VAXBI Level 7 Interrupt VAXBI 7 BVOR 17 VAXBI Offsettable Level 7 Interrupt, VAXBI<13:9> not equal to 0 VAXBI 7 None 16 VAXBI IPINTR 6 Interrupt UINTRCSR 6 BIIC 16 DWMBB BIIC Level 6 Interrupt, VAX
DWMBB Adapter 3.4.1 DWMBB-Detected Error Interrupt Vectors DWMBB-detected error interrupts return vectors from the DWMBB/B module Vector Register (BVR) in response to an XMI IDENT transaction. The vectors are in the format shown in Figure 3–8. The operating system loads a vector value into BVR at system initialization. Figure 3–8 XMI Vector Format 1 5 2 1 0 VECTOR (BVR) MBZ msb−p089−89 3.4.2 VAXBI Node Vector The VAXBI nodes return an interrupt vector without offsettable vectors.
DWMBB Adapter Figure 3–9 VAXBI Node Vector Format 15 9 8 7 6 5 MUST BE ZERO 1 S 2 1 0 Node ID 0 VAXBI Node Vector (<13:9> = zero) PLUS 15 9 VOR BVOR EQUALS 15 9 8 2 1 0 Vector Offset VAXBI Vector<8:2> 0 XMI Vector msb−p090−89 3–22
DWMBB Adapter 3.4.3 Interprocessor Interrupts Interprocessor Interrupts (IPINTRs) are generated by VAXBI nodes targeting the DWMBB. Software must set up the IPINTR Mask Register and the IPINTREN bit in the BCI Control and Status Register. An Interprocessor Interrupt puts a level 6 interrupt onto the VAXBI. The BIIC Interrupt Destination Register causes the interrupt that is received by the DWMBB/B module as a generic VAXBI level 6 interrupt to be passed to the XMI with an IPL of 16 (hex).
DWMBB Adapter 3.4.4.4 Interprocessor-Generated VAXBI Interrupts The DWMBB/B module receives interprocessor interrupts and translates them into generic interrupts if the BIIC is enabled for this function. The generic interrupt is passed onto the XMI with an IPL of 16 (hex). 3.4.4.5 Passive Release of VAXBI Interrupts If the requesting VAXBI node aborts its interrupt request before the XMI commander generates an IDENT transaction at that level, the resulting IDENT on the VAXBI gets NO ACKed.
DWMBB Adapter 3.4.7 IVINTR Transactions Implied Vector Interrupts (IVINTRs) are generated by the DWMBB whenever it detects a condition indicating a possible loss of data, such as parity or ECC errors during DMA or I/O writes. The DWMBB also generates IVINTRs when there is an impending power failure on the VAXBI. All IVINTRs commands generated by the DWMBB have the WRT ERROR INT bit set in the Type field and the target node specified in the Interrupt Destination field.
DWMBB Adapter 3.5 VAXBI Wrapped Read Transactions Both the XMI and the VAXBI have unique and different ways of ordering data read from memory. Wrapped read transactions are used by the DWMBB to order data received from XMI memory to an order that VAXBI devices expect. When a VAXBI DMA read command is received with an address that is not quadword- or octaword-aligned, the DWMBB forces XMI address bits <2:0> to zero when it issues the command to the XMI.
DWMBB Adapter Table 3–5 VAXBI Wrapped Read Transactions Data Length VAXBI A<3:0> Order of Returned Data (first-to-last) Longword X0XX LW-0 (LW-1 is discarded) Longword X1XX LW-1 (LW-0 is discarded) Quadword X0XX LW-0, LW-1 Quadword X1XX LW-1, LW-0 Octaword 00XX LW-0, LW-1, LW-2, LW-3 Octaword 01XX LW-1, LW-2, LW-3, LW-0 Octaword 10XX LW-2, LW-3, LW-0, LW-1 Octaword 11XX LW-3, LW-0, LW-1, LW-2 Hexword Not used on VAXBI Key: X = Don’t care LW-n = Longword n 3–27
DWMBB Adapter 3.6 Lockout Modes The DWMBB has four lockout modes. Lockout Assert Enable (bit <8>) and Lockout Response Enable (bit <7>) (both in the ACSR, Control and Status Register) determine the lockout mode. The four DWMBB lockout modes are: • Mode 0 – The DWMBB ignores the XMI LOCKOUT L signal. • Mode 1 – The DWMBB responds to the XMI LOCKOUT L signal but does not assert it.
DWMBB Adapter 3.6.1 No Assertion and No Response to XMI Lockout Mode The Mode 0 No Assertion and No Response to XMI Lockout Mode causes the DWMBB to ignore the XMI LOCKOUT L signal. The DWMBB does not assert XMI LOCKOUT L when it receives LOC responses to IREAD transactions. It does not respond to the assertion of XMI LOCKOUT L by another XMI node and continues to issue all requests it receives from the VAXBI, including IREADs. 3.6.
DWMBB Adapter • It "times out" with the timeout value that software set in the Lockout Deassertion field, AUTLR<27:24>. The default is 2 to 3 ms. • The DWMBB is reset. While operating in Mode 2 (DWMBA compatibility mode), the DWMBB does not respond to the assertion of the XMI LOCKOUT L signal by another XMI node and continues to issue all requests it receives from the VAXBI, including IREAD transactions. 3.6.
DWMBB Adapter 3.6.5 Programmable Lockout Limit Software loads the Lockout Limit field (AUTLR<31:28>) with a value that determines the number of IREAD transactions attempted by the DWMBB before it asserts the XMI LOCKOUT L signal. When the number of consecutive IREAD attempts on the VAXBI equals or exceeds the value in this field, the DWMBB asserts the XMI LOCKOUT L signal. Table 3–6 lists the values for this field.
DWMBB Adapter 3.6.6 Lockout Deassertion Timer Software loads the Lockout Deassertion field (AUTLR<27:24>) with a value that determines the maximum time that the DWMBB asserts the XMI LOCKOUT L signal. When the DWMBB equals or exceeds this time, the DWMBB deasserts XMI LOCKOUT L regardless of whether a successful IREAD was completed. After power-up or an XMI node reset, the default value is 2 to 3 ms. Table 3–7 lists the values for this field.
DWMBB Adapter 3.7 Commander Arbitration Using Responder Request Two signals are used for arbitrating for the bus, XMI CMD REQ[n] L and XMI RES REQ[n] L. The XMI RES REQ[n] L has a higher priority than the XMI CMD REQ[n] L signal. When the Commander Arbitration Using Responder Request bit is set in the ACSR, Control and Status Register bit <4>, the DWMBB adapter arbitrates for the XMI at a higher priority than XMI commanders.
DWMBB Adapter 3.8 Programmable Timeouts Two programmable timeout limits (see Table 3–8) are available on the DWMBB, a normal limit and a short limit. The short limit is enabled when bit <9> is set in the Control and Status Register.
DWMBB Adapter The DWMBB has two programmable timeout limits: a normal timeout limit that ranges from 0 to 15 ms and a short timeout limit that ranges from 0 to 960 s. The normal timeout limit of 14 to 15 ms is the default value at power-up and node reset. The short timeout limit is set by software. The value is used for both response and retry timeouts, as well as transaction timeouts while waiting for an XMI grant.
DWMBB Adapter 3.9 Programmable VAXBI I/O Window Space The DWMBB can be programmed so that the location of VAXBI I/O window space is independent of the XMI node. This feature is enabled by setting a bit in the Control and Status Register and loading an address in the Utility Register used to calculate the base address of the I/O window space. VAXBI I/O window space is the window for XMI commanders to nodes on the VAXBI. This is a 32-Mbyte range located in the lower 512 Mbytes of XMI I/O address space.
DWMBB Adapter 3.10 ECC Protection on the PMR Data Path The DWMBB can correct single-bit errors and detect double-bit errors on Page Map Registers. If errors come from a single 4-bit RAM, one to four bits can be corrected.
DWMBB Adapter 3.10.1 ECC Errors Detected During I/O PMR Read Accesses If a correctable ECC error occurs during an I/O read of a PMR, the I/O read data is corrected and returned to the requesting XMI node with a CRD function code. The correctable error is logged in AESR and an INTR is issued, if enabled. If an uncorrectable ECC error occurs during an I/O read of a PMR, the uncorrectable I/O read data is sent with good parity and an RER function code to the XMI node that issued the I/O transaction.
DWMBB Adapter 3.11 DWMBB Adapter Registers Two sets of registers are used by the DWMBB: DWMBB registers (residing on both modules of the DWMBB) and VAXBI registers (residing in the BIIC). The DWMBB registers include the XMI required registers and the DWMBB-specific registers.
DWMBB Adapter All VAXBI I/O window space references are stated as bb + nn, where bb is the nodespace starting address on the VAXBI, which is computed by the equation: For 32-bit address: bb = E000 0000 + (200 000 * XMI Node ID) + (2000 * VAXBI Node ID) For 30-bit address: bb = 2000 0000 + (200 000 * XMI Node ID) + (2000 * VAXBI Node ID) If, however, the VAXBI Window Space Enable bit (ACSR<5>) is set, the equation becomes: For 32-bit address: bb = E000 0000 + (200 0000 * AUTLR<13:0>) + (2000 * VAXBI Node ID
DWMBB Adapter Table 3–9 (Cont.
DWMBB Adapter Table 3–11 VAXBI Registers Name Mnemonic Address1 Device Register DTYPE2 bb + 0000 0000 VAXBI Control and Status Register VAXBICSR bb + 0000 0004 Bus Error Register BER bb + 0000 0008 Error Interrupt Control Register EINTRSCR bb + 0000 000C Interrupt Destination Register INTRDES bb + 0000 0010 IPINTR Mask Register IPINTRMSK bb + 0000 0014 Force-Bit IPINTR/STOP Destination Register FIPSDES bb + 0000 0018 IPINTR Source Register IPINTRSRC bb + 0000 001C Starting Addres
DWMBB/A Module Registers Device Register (XDEV) Device Register (XDEV) The Device Register contains information to identify the node and is loaded during node initialization. A zero value indicates an uninitialized node. ADDRESS XMI nodespace base address + 0000 0000 3 1 1 1 6 5 0 Device Revision Device Type (2002) msb−p100−89 bits<31:16> Name: Device Revision Mnemonic: DREV Type: RO Identifies the functional revision level of the module in hexadecimal.
DWMBB/A Module Registers Device Register (XDEV) bits<15:0> Name: Device Type Mnemonic: DTYPE Type: RO, 2002 (hex) Identifies the type of node. DTYPE is 2002 (hex) for the DWMBB/A module.
DWMBB/A Module Registers Bus Error Register (XBER) Bus Error Register (XBER) The Bus Error Register contains error status on a failed XMI transaction. This status includes the failed commander ID and an error bit that indicates the type of error that occurred. This status remains locked up until software resets the error bit(s).
DWMBB/A Module Registers Bus Error Register (XBER) bit<31> Name: Error Summary Mnemonic: ES Type: RO, 1 ES represents the logical OR of the error bits in this register.
DWMBB/A Module Registers Bus Error Register (XBER) bit<29> Name: Node Halt Mnemonic: NHALT Type: RO, 0 Reserved; must be zero. bit<28> Name: XMI BAD Mnemonic: XBAD Type: RO, 0 Reserved; must be zero. bit<27> Name: Corrected Confirmation Mnemonic: CC Type: R/W1C, 0 CC sets when the DWMBB detects a single-bit CNF error. Single-bit CNF errors are automatically corrected by the XCLOCK chip in the XMI Corner.
DWMBB/A Module Registers Bus Error Register (XBER) bit<24> Name: Inconsistent Parity Error Mnemonic: IPE Type: R/W1C, 0 IPE, when set, indicates that the node detected a parity error on an XMI cycle and that at least one other node (the responder) detected good parity during the cycle (the confirmation for the cycle was ACK). This bit sets for all XMI inconsistent parity errors, regardless of whether the XMI cycle targeted this node.
DWMBB/A Module Registers Bus Error Register (XBER) bit<19> Name: Corrected Read Data Mnemonic: CRD Type: R/W1C, 0 When set, CRD indicates that the DWMBB received a CRDn read response. bit<18> Name: No Read Response Mnemonic: NRR Type: R/W1C, 0 When set, NRR indicates that a read transaction initiated by the DWMBB failed due to a read response timeout.
DWMBB/A Module Registers Bus Error Register (XBER) bit<15> Name: Command NO ACK Mnemonic: CNAK Type: R/W1C, 0 When set, CNAK indicates that a command/address cycle transmitted by the DWMBB received a NO ACK confirmation and all reattempts have failed (retry timeout). This can be caused by either a reference to a nonexistent memory location or a command cycle parity error. This bit is set only if all retries fail and TTO sets.
DWMBB/A Module Registers Bus Error Register (XBER) bit<12> Name: Node-Specific Error Summary Mnemonic: NSES Type: RO, 0 When set, NSES indicates that a node-specific error condition was detected.
DWMBB/A Module Registers Bus Error Register (XBER) bit<10> Name: Selt-Test Fail Mnemonic: STF Type: R/W1C, 1 When set, STF indicates that the DWMBB has not yet passed its selftest. This bit is cleared by the CPU node that executed the DWMBB self-test when the DWMBB passes its self-test. bits<9:4> Name: Failing Commander ID Mnemonic: FCID Type: RO, 0 The Failing Commander ID field logs the commander ID of a failing transaction. FCID sets only if all reattempts fail.
DWMBB/A Module Registers Failing Address Register (XFADR) Failing Address Register (XFADR) The Failing Address Register logs address and length information associated with a failing transaction. The DWMBB locks this register only if the transaction fails.
DWMBB/A Module Registers Responder Error Address Register (AREAR) Responder Error Address Register (AREAR) AREAR logs the failing address of an I/O write, read, or IDENT from an XMI commander node directed to the DWMBB or the VAXBI. AREAR is loaded when the DWMBB ACKs the XMI’s C/A cycle. AREAR is locked when the DWMBB is unable to complete the requested operation because of a detected error.
DWMBB/A Module Registers Responder Error Address Register (AREAR) bits<29:0> Name: Responder Failing Address Mnemonic: None Type: RO, 0 XMI D<29:0> is loaded into the DWMBB during the cycle that the DWMBB accepts the C/A cycle from an XMI commander. It locks only if the transaction fails and unlocks when all the error conditions clear.
DWMBB/A Module Registers Error Summary Register (AESR) Error Summary Register (AESR) AESR is used to capture DWMBB/A module-related error conditions.
DWMBB/A Module Registers Error Summary Register (AESR) bits<25:20> Name: Responder Failing ID Mnemonic: RFID Type: RO, 0 RFID logs the XMI node ID of a failed DWMBB I/O write, I/O read, or XMI IDENT transaction. The DWMBB loads this field during the C/A cycle that the DWMBB accepts. RFID locks if the transaction fails and unlocks when the error condition clears.
DWMBB/A Module Registers Error Summary Register (AESR) bit<13> Name: Correctable PMR ECC Error Mnemonic: CORR PMR ECC ERR Type: R/W1C, 0 CORR PMR ECC ERR indicates, when set, that a correctable ECC error occurred during an I/O read access to a PMR. The assertion of this bit locks the Responder Error Address Register (AREAR).
DWMBB/A Module Registers Error Summary Register (AESR) bit<10> Name: Correctable DMA ECC Error Mnemonic: CORR DMA ECC ERR Type: R/W1C, 0 CORR DMA ECC ERR indicates, when set, that a fetch from the PMR during a DMA address translation detected and corrected an error. The assertion of this bit locks the ABEAR. CORR DMA ECC ERR sets only when the DWMBB is operating in an address translation mode. When this bit sets, an interrupt is generated if INTR CORR ECC ERR (AIMR<10>) is set.
DWMBB/A Module Registers Error Summary Register (AESR) If the transaction was a DMA write, or otherwise might cause a data loss, an IVINTR with WRT ERROR INT set in the Type field is generated if Enable IVINTR Transactions (AIMR<31>) is set. bit<7> Name: Internal Error Mnemonic: None Type: R/W1C, 0 The Internal Error bit sets to indicate that an UNEXPLAINED internal error to the DWMBB/A module gate array was detected, generally a hardware problem where control logic encountered UNDEFINED conditions.
DWMBB/A Module Registers Error Summary Register (AESR) bit<5> Name: BCI AC LO Mnemonic: None Type: R/W1C, 1 The BCI AC LO bit sets when VAXBI power falls below specifications, as indicated by an asserted BCI AC LO L signal (asserted = one). The DWMBB issues an IVINTR with WRT ERROR INT set in the Type field when BCI AC LO asserts, if Enable IVINTR Transactions (AIMR<31>) is set, so that software can determine the cause of this IVINTR transaction.
DWMBB/A Module Registers Error Summary Register (AESR) bit<3> Name: IBUS DMA-A C/A Parity Error Mnemonic: IBUS DMA-A CA PE Type: R/W1C, 0 IBUS DMA-A C/A Parity Error sets when the DWMBB/A module detects a parity error on the IBUS when the DWMBB/B module was loading a DMA-A data buffer C/A location. The DWMBB issues an IVINTR with WRT ERROR INT set in the Type field when IBUS DMA-A C/A Parity Error asserts and the failing DMA transaction is a write or interrupt.
DWMBB/A Module Registers Error Summary Register (AESR) bit<0> Name: IBUS I/O Read Data Parity Error Mnemonic: IBUS I/O RD PE Type: R/W1C, 0 IBUS I/O Read Data Parity Error sets when the DWMBB/A module detects a parity error on the IBUS when the DWMBB/B module was loading the I/O data location during an XMI commander-initiated I/O read or IDENT. The DWMBB issues a Read Error Response (RER) to the commander when the error occurs during an I/O read transaction.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) Interrupt Mask Register (AIMR) AIMR enables/disables the generation of an error interrupt transaction when the corresponding error bit in either the DWMBB/A module’s Bus Error Register (XBER) or the DWMBB/A module’s Error Summary Register (AESR) is set.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<31> Name: Enable IVINTR Transactions Mnemonic: None Type: R/W, 0 When Enable IVINTR Transactions is set and IVINTR Destination Register is properly configured, IVINTRs are enabled and can be issued on the XMI bus.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<27> Name: Interrupt on Corrected Confirmation Mnemonic: INTR CC Type: R/W, 0 When Interrupt on Corrected Confirmation is set, the DWMBB generates an interrupt if Corrected Confirmation (XBER<27>) sets. bits<26:25> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<21> Name: Interrupt on Read/IDENT NO ACK Mnemonic: INTR RIDNAK Type: R/W, 0 When Interrupt on Read/IDENT NO ACK is set, the DWMBB generates an interrupt if Read/IDENT NO ACK (XBER<21>) sets. bit<20> Name: Interrupt on Write Data NO ACK Mnemonic: INTR WDNAK Type: R/W, 0 When Interrupt on Write Data NO ACK is set, the DWMBB generates an interrupt if Write Data NO ACK (XBER<20>) sets.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<16> Name: Interrupt on Read Error Response Mnemonic: INTR RER Type: R/W, 0 When Interrupt on Read Error Response is set, the DWMBB generates an interrupt if Read Error Response (XBER<16>) sets. bit<15> Name: Interrupt on Command NO ACK Mnemonic: INTR CNAK Type: R/W, 0 When Interrupt on Command NO ACK is set, the DWMBB generates an interrupt if Command NO ACK (XBER<15>) sets.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<10> Name: Interrupt on Correctable ECC Error Mnemonic: INTR CORR ECC ERR Type: R/W, 0 When Interrupt on Correctable ECC Error is set, the DWMBB generates an interrupt if Correctable PMR ECC Error (AESR<13>) or Correctable DMA ECC Error (AESR<10>) sets.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<5> Name: Interrupt on BCI AC LO Mnemonic: INTR BCI AC LO Type: R/W, 0 When Interrupt on BCI AC LO is set, the DWMBB generates an interrupt if BCI AC LO (AESR<5>) sets. bit<4> Name: Interrupt on DMA-A Data Parity Error Mnemonic: INTR DMA-A DATA PE Type: R/W, 0 When the Interrupt on DMA-A Data Parity Error bit is set, the DWMBB generates an interrupt if IBUS DMA-A Data Parity Error (AESR<4>) sets.
DWMBB/A Module Registers Interrupt Mask Register (AIMR) bit<0> Name: Interrupt on IBUS I/O Read Data Parity Error Mnemonic: INTR I/O RD PE Type: R/W, 0 When the Interrupt on IBUS I/O Read Data Parity Error bit is set, the DWMBB generates an interrupt if IBUS I/O Read Data Parity Error (AESR<0>) sets.
DWMBB/A Module Registers Implied Vector Interrupt Destination/Diagnostic Register (AIVINTR) Implied Vector Interrupt Destination/Diagnostic Register (AIVINTR) The AIVINTR is used during DWMBB-initiated IVINTR transactions and diagnostics. ADDRESS XMI nodespace base address + 0000 0018 AIVINTR, when used during DWMBB-initiated IVINTR transactions: 3 1 1 1 6 5 MUST BE ZERO 0 IVINTR Destination msb−p081−89 bits<31:16> Name: Reserved Mnemonic: None Type: R/W Reserved; must be zero.
DWMBB/A Module Registers Implied Vector Interrupt Destination/Diagnostic Register (AIVINTR) 1 AIVINTR, when used during diagnostics: 3 1 0 Diagnostic Read or Write msb−p080−89 bits<31:0> Name: Diagnostic Read or Write Mnemonic: None Type: R/W The Diagnostic Read or Write field is used by diagnostic routines to verify the integrity of the DWMBB/A module’s main data path inside the DWMBB/A module gate array.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) Diagnostic 1 Register (ADG1) Diagnostics use ADG1 to test parity and other features in the DWMBB/A module and the IBUS.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) bit<30> Name: Receive Lockout Status Mnemonic: RCV LOCKOUT STATUS Type: R/W1C, 0 Receive Lockout Status sets on the first assertion of the XCI RECEIVE LOCKOUT L signal. It can be cleared only after Force Transmit Lockout (ADG1<10> is cleared. bit<29> Name: Transmit Lockout Status Mnemonic: XMIT LOCKOUT STATUS Type: R/W1C, 0 Transmit Lockout Status sets on the first assertion of the XCI TRANSMIT LOCKOUT L signal.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) If Force Data NO ACK is set and a DMA read is received by the DWMBB, the DWMBB times out after the DMA read command has been issued on the XMI and before the DMA read data is returned, causing NRR to set.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) bit<11> Name: Force ECC Error Mnemonic: None Type: R/W, 0 Force ECC Error, when set, forces an ECC error to occur on any transaction that reads the contents of a PMR. The error could be either correctable or uncorrectable, depending on the data and check bits stored in the selected PMR location.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) When DWMBB/A Flip Failing Address Bit<1> is used with Force DMA-A Buffer Busy (ADG1<5>) and Force DMA-B Buffer Busy (ADG1<4>), both DMA data buffers can be thoroughly tested. bit<8> Name: DWMBB/A Flip Address Bit<29> Mnemonic: DWMBB/A FLIP ADDR BIT<29> Type: RO DWMBB/A Flip Address Bit<29> causes I/O C/A bit<29> and the C/A parity bit to be flipped for I/O transactions sent to the DWMBB /B module.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) bit<5> Name: Force DMA-A Buffer Busy Mnemonic: FORCE DMA-A BUSY Type: R/W, 0 When set, the Force DMA-A Buffer Busy bit forces the DMA buffer control logic to place the DMA-A buffer into the busy state, forcing all DMA traffic through the DMA-B buffer. CAUTION: If both ADG1<5> and ADG1<4> are set, all legal DMA transactions stall.
DWMBB/A Module Registers Diagnostic 1 Register (ADG1) bit<1> Name: Interrupt Sent Status Mnemonic: INTR SENT Type: R/W1C, 0 Interrupt Sent Status reflects the status of the XMI Error Bit Sent signal, which is issued to the DWMBB/B module to generate an INTR. Interrupt Sent Status is used by diagnostics in DWMBB/A module loopback mode to ensure that the AIMR interrupt enable bits are working properly.
DWMBB/A Module Registers Utility Register (AUTLR) Utility Register (AUTLR) The Utility Register contains fields for the software programmable selection of timeout values and for moving the VAXBI Window Address Space to an I/O address range other than the power-up or reset default value.
DWMBB/A Module Registers Utility Register (AUTLR) LLIM (hex) IREAD Attempts B 11 C 12 D 13 E 14 F 15 bits<27:24> Name: Lockout Deassertion Mnemonic: LDEASRT Type: R/W, 3 (hex), which corresponds to 2–3 ms Lockout Deassertion determines the maximum time that the DWMBB asserts the XMI LOCKOUT L signal. When the DWMBB equals or exceeds this time, the DWMBB deasserts XMI LOCKOUT L regardless of whether or not a successful IREAD was completed.
DWMBB/A Module Registers Utility Register (AUTLR) bits<23:20> Name: Timeout Limit Mnemonic: TLIM Type: R/W, F (hex), which corresponds to 14–15 ms Timeout Limit determines the time that the DWMBB retries a transaction on the XMI or waits for returning read data in response to a successful XMI read command. When the value is exceeded, the transaction aborts and Transaction Timeout (XBER<13>) sets.
DWMBB/A Module Registers Utility Register (AUTLR) bits<19:18> Name: Mapping Register Mode Enable Mnemonic: MR MD Type: R/W, 0 The Mapping Register Mode Enable field determines the operating mode of the DWMBB as follows: MR MD (hex) Operating Mode 0 DWMBA compatibility mode (default) 1 40-bit VAX address translation using 512-byte page sizes 2 40-bit address translation using 4-Kbyte page sizes 3 40-bit address translation using 8-Kbyte page sizes bits<17:14> Name: Reserved Mnemonic: None
DWMBB/A Module Registers Utility Register (AUTLR) bits<13:0> Name: VAXBI Window Space Mnemonic: BIWIN Type: R/W, 0 VAXBI Window Space enables software to reconfigure the VAXBI I/O address space to any 32-Mbyte address range within the 512-Mbyte I/O address space. The base address of this window space normally depends on the XMI node ID and the VAXBI node ID.
DWMBB/A Module Registers Control and Status Register (ACSR) Control and Status Register (ACSR) The Control and Status Register contains DWMBB/A module operational information.
DWMBB/A Module Registers Control and Status Register (ACSR) bit<30> Name: Control Reset Mnemonic: CTL RESET Type: WO, 0 Control Reset, when set, causes the DWMBB to execute a control reset even if it is in a hung state or busy processing another transaction. A control reset does the following: • Resets all logic on the DWMBB/A module except the I/O registers (including the PMRs) to an initialized (power-up) state. This allows XMI operation to not be affected by the DWMBB/A module’s reset.
DWMBB/A Module Registers Control and Status Register (ACSR) bits<16:10> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero. bit<9> Name: Short Timeout Enable Mnemonic: SHORT TMO ENA Type: R/W, 0 Short Timeout Enable, when set, enables the DWMBB to use the smaller timeout range of from 0 to 960 s instead of the normal timeout range of from 0 to 15 ms.
DWMBB/A Module Registers Control and Status Register (ACSR) bit<5> Name: VAXBI Window Space Enable Mnemonic: BIWIN ENA Type: R/W, 0 VAXBI Window Space Enable, when set, enables the VAXBI Window Space field (AUTLR<13:0>), allowing software to reconfigure the VAXBI I/O address space into any 32-Mbyte address of the 512-Mbyte I/O address space.
DWMBB/A Module Registers Control and Status Register (ACSR) bit<1> Name: Return Vector Disable Mnemonic: RETURN VECTOR DIS Type: R/W, 0 Return Vector Disable, when set, prevents the DWMBB from returning the contents of the Return Vector Register in response to an unsolicited or failed IDENT. Instead, the DWMBB issues a Read Error Response to the XMI. bit<0> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero.
DWMBB/A Module Registers Return Vector Register (ARVR) Return Vector Register (ARVR) The DWMBB returns the vector in ARVR<15:2> when the module either receives an unsolicited IDENT or receives an IDENT that fails on the VAXBI. This feature of the DWMBB is controlled by the Return Vector Disable bit in the Control and Status Register (ACSR <1>). When the Return Vector Disable bit is set, the DWMBB responds with an RER.
DWMBB/A Module Registers Failing Address Extension Register (XFAER) Failing Address Extension Register (XFAER) XFAER logs the address extension, command, and mask information associated with a failed XMI commander transaction. The DWMBB locks XFAER only if the transaction fails.
DWMBB/A Module Registers Failing Address Extension Register (XFAER) bits<25:16> Name: Failing Address Extension Mnemonic: None Type: RO, 0 Failing Address Extension logs XMI D<57:48> during the C/A cycle of a failed XMI commander transaction or bits<38:29> of the address specified in the transaction for DMA reads and DMA writes.
DWMBB/A Module Registers VAXBI Error Address Register (ABEAR) VAXBI Error Address Register (ABEAR) ABEAR logs address and length information of failed IBUS DMA and interrupt transactions that are detected by the DWMBB/A module. The logged addresses are in VAXBI format.
DWMBB/A Module Registers VAXBI Error Address Register (ABEAR) bits<29:0> Name: Failing VAXBI Address Mnemonic: None Type: RO, 0 The Failing VAXBI Address field logs IBUS D<29:0> during a failed IBUS DMA or interrupt transaction.
DWMBB/A Module Registers Page Map Registers (PMRs) Page Map Registers (PMRs) The DWMBB/A module contains 64K page map registers which are used to store page frame numbers (PFNs) for extended address translation. The format of the PMRs is identical.
DWMBB/A Module Registers Page Map Registers (PMRs) bits<29:0> Name: Page Frame Number Mnemonic: PFN Type: R/W, 0 This field stores a page frame number for address translation for mapping between the XMI and the VAXBI. When the DWMBB is in any of the address translation modes, system software must load a valid PFN entry into this field for the associated PMR of every VAXBI page it queues for transfer.
DWMBB/B Module Registers Control and Status Register (BCSR) Control and Status Register (BCSR) BCSR contains DWMBB/B module operational control and status bits.
DWMBB/B Module Registers Control and Status Register (BCSR) VAXBI BAD sets when BI BAD L deasserts to indicate that all VAXBI nodes have passed self-test, except for the DWMBB/B module, where it means that the BIIC passed its internal self-test. bit<3> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero.
DWMBB/B Module Registers Error Summary Register (BESR) Error Summary Register (BESR) The BESR contains status bits for errors detected by the DWMBB/B module.
DWMBB/B Module Registers Error Summary Register (BESR) bit<12> Name: DWMBB Interrupt-Pending Status Mnemonic: XBI INT PEND Type: RO, 0 DWMBB Interrupt-Pending Status, when set, indicates that a DWMBB interrupt is pending. bits<11:8> Name: VAXBI Interrupt-Pending Status Mnemonic: BR7–BR4 Type: RO, 0 The VAXBI Interrupt-Pending Status field sets to indicate that one or more of the VAXBI interrupt-pending flip-flops is set.
DWMBB/B Module Registers Error Summary Register (BESR) bit<5> Name: Slave Sequencer Transaction Failed Mnemonic: None Type: RO, 0 Slave Sequencer Transaction Failed, when set with BESR<0>, indicates that an IBUS parity error occurred while the slave sequencer had control of the IBUS during a read data fetch from the DWMBB/A module.
DWMBB/B Module Registers Error Summary Register (BESR) bit<2> Name: VAXBI Interlock Read Failed Mnemonic: None Type: R/W1C, 0 VAXBI Interlock Read Failed sets to indicate that a VAXBI-to-XMI memory Interlock Read operation failed to successfully complete on the VAXBI. When this error occurs, it is probable that the lock set in XMI memory will not be unlocked by the VAXBI device that issued the Interlock Read.
DWMBB/B Module Registers Error Summary Register (BESR) bit<0> Name: DWMBB/B-Detected IBUS Parity Error Mnemonic: B IBUS PE Type: R/W1C, 0 DWMBB/B-Detected IBUS Parity Error sets if the DWMBB/B module detects an IBUS parity error while fetching information from the DWMBB/A module. The setting of DWMBB/B-Detected IBUS Parity Error locks BESR<6:4> and, if the fetch was for DMA read return data, the Timeout Address Register is also locked.
DWMBB/B Module Registers Interrupt Destination Register (BIDR) Interrupt Destination Register (BIDR) The Interrupt Destination Register is used in two ways: First the DWMBB uses the lower sixteen bits to identify which node is to receive an error/status interrupt. Second, diagnostics use the entire register to verify the data path integrity of the DWMBB/B module.
DWMBB/B Module Registers Timeout Address Register (BTIM) Timeout Address Register (BTIM) The Timeout Address Register is loaded each time a DMA command/address is latched off the VAXBI. BTIM locks when (1) a VAXBI-to-XMI memory Interlock Read fails, causing the VAXBI Interlock Read Failed bit (BESR<2>) to set, or (2) a VAXBI-to-XMI memory read-type fails, causing the IBUS Parity Error bit (BESR<0>) to be set by the DWMBB/B.
DWMBB/B Module Registers Vector Offset Register (BVOR) Vector Offset Register (BVOR) The Vector Offset Register contains a value that is concatenated with the VAXBI device-supplied vector, if bits<13:9> of the VAXBI-supplied vector are equal to zero. ADDRESS XMI nodespace base address + 0000 0050 3 1 1 1 6 5 MUST BE ZERO 9 8 0 MUST BE ZERO DWMBB/B Vector Offset Register (VOR) msb−p117−89 bits<31:16> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero.
DWMBB/B Module Registers Vector Register (BVR) Vector Register (BVR) System software loads the BVR with the vector to be transmitted to the node responding to the DWMBB’s interrupt request. ADDRESS XMI nodespace base address + 0000 0054 3 1 1 1 6 5 MUST BE ZERO 2 1 0 DWMBB Vector MBZ msb−p118−89 bits<31:16> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero.
DWMBB/B Module Registers Diagnostic Control Register 1 (BDCR1) Diagnostic Control Register 1 (BDCR1) BDCR1 is used by diagnostics to perform various diagnostic functions on the DWMBB/B module, ensuring that its hardware operates properly.
DWMBB/B Module Registers Diagnostic Control Register 1 (BDCR1) bit<5> Name: Reserved Mnemonic: None Type: RO, 0 Reserved; must be zero. bit<4> Name: DWMBB/B Flip Address Bit<29> Mnemonic: B Flip A29 Type: R/W, 0 Setting DWMBB/B Flip Address Bit<29> inverts the state of Address<29> and BCI parity after the I/O C/A has been fetched and decoded by the DWMBB/B module. The new address, which now points to XMI memory space, is issued to the VAXBI.
DWMBB/B Module Registers Reserved Register (BRSVD) Reserved Register (BRSVD) The Reserved Register is an undefined register that is reserved for future use. Reads to this register return UNDEFINED data with correct parity. Writes to this register appear to complete successfully. ADDRESS XMI nodespace base address + 0000 005C 3 1 0 RESERVED msb−p120−89 bits<31:0> Name: Reserved Register Mnemonic: BRSVD Type: Undefined The reserved register bits are reserved for future use.
VAXBI Registers Device Register (DTYPE) Device Register (DTYPE) The VAXBI Device Register is loaded during self-test by console code with the DWMBB VAXBI device type and by the revision select logic with the revision level. ADDRESS VAXBI nodespace base address + 0000 0000 3 1 1 1 6 5 0 Device Revision Device Type (210F) msb−p121−89 bits<31:16> Name: Device Revision Mnemonic: DREV Type: R/W, 0 Identifies the revision level of the device.
DWMBB Adapter 3.12 Error Handling The DWMBB detects errors on the XMI, the VAXBI, the IBUS, and in the page map register RAMs. DWMBB error handling accomplishes the following: • Captures error information for error analysis • Prevents errors from propagating by aborting error-causing transactions • Facilitates software recovery Error generation and checking is performed on the DWMBB, on both ports of the CPU, on DMA-A and DMA-B register files, and on the IBUS data path between the modules.
DWMBB Adapter 3.12.1 Error Interrupts The DWMBB generates either Interrupts (INTRs) or Implied Vector Interrupts (IVINTRs) in response to detected errors. An INTR is generated at IPL 17 when INTRs are enabled. These INTRs are serviced before IPL 17 interrupts originating from the VAXBI. The DWMBB/B module generates all INTRs. If the DWMBB/A module detects an error condition requiring an INTR and the appropriate interrupt enable bit is set, it asserts an interrupt error status flag on the IBUS.
DWMBB Adapter 3.12.3 Multiple Errors When an error is detected, the registers listed in Table 3–14 are locked and cannot be updated until the corresponding error bits have been cleared by an XMI commander node. If another error occurs before the first error is processed, a status bit is set to indicate the occurrence of multiple errors. The multiple error flags are Multiple Errors (AESR<14>) and Multiple CPU Errors (BESR<7>).
DWMBB Adapter 3.12.4.1 Invalid VAXBI Address An invalid VAXBI address error can occur at any time (while the DWMBB is in DWMBA compatibility mode as well as in the address translation modes). The DWMBB/A module checks the appropriate VAXBI address bits (as shown in Table 3–15) to determine the validity of the address during a DMA read or write transaction. These address bits must be zero to be valid.
DWMBB Adapter 3.12.4.3 ECC Errors on PMR Data During DMA Address Translation The DWMBB/A module uses ECC to determine if there is an error on the data being read from the PMR. These ECC errors can be correctable or uncorrectable. 3.12.4.3.
DWMBB Adapter 3.12.4.4 ECC Errors on PMR Data During I/O Reads to PMR The DWMBB/A module uses ECC to determine if there is an error on the data being read from the PMR. These ECC errors can be correctable or uncorrectable. 3.12.4.4.1 Uncorrectable ECC Errors If an uncorrectable ECC error is found, the DWMBB does the following: 3.12.4.4.
DWMBB Adapter 3.12.5 IBUS Parity Errors The DWMBB detects IBUS parity errors on all cycles. The DWMBB/A module detects IBUS parity errors on the following cycles: • DMA write C/A or INTR C/A • DMA write data • DMA read C/A • I/O read data or IDENT vector The DWMBB/B module detects IBUS parity errors on the following cycles: 3.12.5.1 3.12.5.
DWMBB Adapter • 3.12.5.3 3.12.5.4 3.12.5.
DWMBB Adapter • 3.12.5.
DWMBB Adapter 3.12.5.
DWMBB Adapter 3.12.5.11 Undecodable DMA C/A with no IBUS Parity Error Detected If all the following occur, • A DMA C/A cycle is loaded into the DWMBB/A module. • The command field is undecodable. • No parity error is detected. • The DWMBB/B module does not nullify the DMA transaction. The DWMBB/A module sets Internal Error (AESR<7>), causing an IVINTR to be issued, if IVINTRs are enabled, and the DMA address is logged in ABEAR<29:0>.
DWMBB Adapter 3.12.6 XMI Errors Table 3–16 lists the error bits and their descriptions for XMI-detected errors that the DWMBB sets when the error occurs. Table 3–16 XMI Error Bits Bit Location Description Transaction Timeout (TTO) XBER<13> Sets when a DWMBB-initiated DMA transaction times out waiting for a response from a responder node, waiting to get an XMI grant, or until the retry limit is reached. Once TTO sets, the DMA transaction aborts and XMI error bits latch.
DWMBB Adapter 3.12.6.1 DMA Write C/A XMI Error The DWMBB operates as an XMI commander during a DMA write transaction. It starts a retry counter as it begins executing the DMA write by arbitrating for the XMI. Errors encountered while transmitting the DMA write cause retries until it completes successfully or the retry counter times out, which causes the DMA write to be considered a failure.
DWMBB Adapter 3.12.6.5 Parity Errors on the XMI The DWMBB sets PE whenever it detects a parity error on an XMI cycle and sets IPE whenever it detects a parity error on an XMI cycle that is ACKed. If a parity error is detected on the XMI during an I/O write C/A, I/O read C/A, I/O write data, or an IDENT cycle, the transaction is NO ACKed and PE set. An INTR is generated if Interrupt on Parity Error (AIMR<23>) is set.
DWMBB Adapter 3.12.7 VAXBI Errors VAXBI errors originate on either a VAXBI device or the VAXBI bus. These errors are detected by the DWMBB/B module’s BIIC and by other VAXBI devices. Error status bits are set in the BIIC’s Bus Error Register (BER). If a failure is detected during an I/O write transaction on the VAXBI, it is considered a disconnected write.
DWMBB Adapter 3.12.8 Miscellaneous Errors These errors originate on the control logic and during DWMBB operation but do not pertain to the data paths. 3.12.8.1 Impending Power Fail The BCI AC LO L signal asserts to warn of an impending power fail on the VAXBI. This sets BCI AC LO (AESR<5>), causing the DWMBB to generate an IVINTR on the XMI if Enable IVINTR Transactions (AIMR<31>) is set. The DWMBB completes any current transaction in progress and stops processing further transactions. 3.12.8.
DWMBB Adapter 3.12.8.4 DMA Read Data Parity Error during DWMBB/A Module Loopback If an XMI parity error is detected on DMA read data during a loopback mode, PE and either RSE, NRR, or TTO set. An RER is returned to the originating XMI node and INTRs are generated if the appropriate enable bits in AIMR are set. 3.12.8.
DWMBB Adapter 3.13 DWMBB Initialization This section discusses the DWMBB initialization. The four ways to reset the DWMBB are: • Normal Power-Up—When the system is powered up, XMI AC LO L and XMI DC LO L are sequenced so that all XMI nodes are reset. • System Reset—The XMI emulates a power-up sequence by asserting the XMI RESET L line, causing the power supply to sequence XMI AC LO L and XMI DC LO L as in a "real" power-up. The XMI does not differentiate between a "real" power-up and a system reset.
DWMBB Adapter Software, once in DWMBA compatibility mode, loads the appropriate registers for enabling interrupts and DMA transfers to/from memory. Software can also change the operating mode to one of the address translation modes. 3.13.1 DWMBB/A Module Initialization Sequence When the DWMBB/A module detects a reset condition, it does the following: • Aborts any transaction in progress.
DWMBB Adapter are lost, permitting the reading of CSRs, which might help determine the cause of an error. Control Reset is a diagnostic feature that is not to be used in normal operation. 3.13.
DWMBB Adapter 3.14 Diagnostic Features The DWMBB diagnostic features provide the capability to observe, test, and verify logic without the use of test equipment, such as external loopback connectors. The following sections describe and explain these features.
DWMBB Adapter 3.14.1 Internal Loopback Modes Loopback modes help isolate a fault to an area of logic by enabling software to test segments of the main data path. The three types of DWMBB loopbacks are: • DWMBB/A module loopback — Data path to the DWMBB/A module • BIIC loopback — Data path includes DWMBB/A module and DWMBB/B module • DMA loopback — Data path includes DWMBB/A module, DWMBB/B module, and the VAXBI The three DWMBB loopbacks are illustrated in Figure 3–14.
DWMBB Adapter While in DWMBB/A module loopback mode, the IBUS drivers are turned off and I/O commands from the XMI are looped back to the IBUS DMA input command/address latches in the DWMBB/A module gate array. If a parity error or PFN error is found during the C/A cycle, the appropriate bits set in AESR. I/O write data does not loop back through the gate array transceivers but is transferred internally in the gate array, taking the same path that the PMR write data takes.
DWMBB Adapter D<12:8> are all zeros to indicate that one of the BIIC internal registers is selected. D<7:0> specify the register, the same as during a VAXBI transaction. 3.14.1.3 DMA Loopback During DMA loopback mode, the main data path includes the DWMBB/A module, the IBUS, the DWMBB/B module, and the VAXBI. The mode is entered by setting DWMBB/A Flip Address Bit<29> (BDCR1<4>).
DWMBB Adapter 3.14.2 DWMBB/A Module Gate Array Transaction Register Files Testing The DWMBB/A module gate array transaction register files (TRF) contain I/O buffers and DMA buffers. The transaction register files have two sections: the transmit registers and the receive registers. Both files represent a total of 17 buffers, as shown in Figure 3–15 and Figure 3–16. The DWMBB/A module is nonoperational if the I/O buffers fail.
DWMBB Adapter Figure 3–16 DWMBB/A Module Receive Registers ADDRESS BUFFERS IM FADDR<3:0> = 0 I/O C/A BUFFER IM FADDR<3:0> = 1 I/O DATA BUFFER IM FADDR<3:0> = 4 DMA−A LONGWORD DATA 1 IM FADDR<3:0> = 5 DMA−A LONGWORD DATA 2 IM FADDR<3:0> = 6 DMA−A LONGWORD DATA 3 IM FADDR<3:0> = 7 DMA−A LONGWORD DATA 4 msb−p097−89 Table 3–19 Diagnostic Bits That Test DMA Buffers in Loopback Mode Diagnostic Bit Location Description DWMBB/A Loopback Enable ADG1<7> When set, places the DWMBB/A module in DWMB
DWMBB Adapter Table 3–19 (Cont.) Diagnostic Bits That Test DMA Buffers in Loopback Mode Diagnostic Bit Location Description DWMBB/A Flip Failing Address Bit<1> ADG1<9> DWMBB/A Flip Failing Address Bit<1> is used with Force Octaword Transfer and XMI I/O Command/Address Bit<2> to allow diagnostics to access and test all the transmit register files and receive register files. DWMBB/A Flip Failing Address Bit<1> permits the use of the data buffers that are used for transfers greater than a quadword.
DWMBB Adapter Table 3–19 (Cont.) Diagnostic Bits That Test DMA Buffers in Loopback Mode Diagnostic Bit Location Description Force DMA-A Buffer Busy Force DMA-B Buffer Busy ADG1<5> ADG1<4> When set, forces the DMA buffer control logic to place either the DMA-A buffer or the DMA-B buffer into the busy state, forcing all DMA traffic through the other buffer. Force DMA-A Buffer Busy and Force DMA-B Buffer Busy ensure that both sets of DMA buffers get tested.
DWMBB Adapter 3.14.2.1 Executing DMA Writes and Reads in Loopback Mode Diagnostic software tests all the DMA data and C/A buffers in the transaction register file by using DMA loopback mode or DWMBB/A module loopback mode to send DMA write data to any one of the longwordlength locations in either of the DMA data buffers. The data is then written to XMI memory, where it is checked for accuracy. DMA read commands are used to verify the data that was sent to XMI memory.
DWMBB Adapter 2 Either a. Set DWMBB/A Loopback Enable and Flip Address Bit<29> to put the DWMBB in DWMBB/A module loopback mode and to convert I/O transactions targeted for the DWMBB/B module or a VAXBI node into a DMA transaction targeted for XMI memory. Or b. Set DWMBB/B Flip Address Bit<29> to put the DWMBB into a DMA loopback mode and to convert I/O transactions targeted for a VAXBI node into a DMA transaction targeted for XMI memory.
DWMBB Adapter 3.14.2.2 Transaction Register File in Loopback Mode Using DMA Writes and Reads Figure 3–17 shows a way diagnostic software can use the diagnostic bits and DMA loopback write/read pairs to test the DMA transmit and receive registers as well as most of the control and data path of the DWMBB. Figure 3–17 Testing the DMA Transmit and Receive Registers 1. Do an I/O write to ADG1 to put DWMBB in DWMBB/A loopback mode: I/O write − I/O data 2.
DWMBB Adapter Figure 3–17 (Cont.) Testing the DMA Transmit and Receive Registers 5. Do a DMA loopback write/read pair with I/O Address Bit<2> set to zero: I/O write − I/O address = XX XXDE FED0#16 − I/O data = 1111 1111#16 I/O read − Same address as I/O write LOCATIONS TESTED: TRANSMIT 6.
DWMBB Adapter 3.14.3 Forcing Bad Parity Forcing bad parity is used by diagnostic software to check the integrity of the data paths by verifying the proper operation of the DWMBB parity logic. All data paths in the DWMBB use odd parity except for the XMI, which uses even parity, and the PMR data path, which has ECC protection. Parity is propagated on all data cyles and on all C/A cycles except DMA C/A cycles during address translation, where parity is checked and then regenerated. 3.14.3.
DWMBB Adapter 3.14.3.2 3.14.4 Forcing Bad Parity on the BCI Forcing bad parity on the BCI, by using Force BCI Bad Parity (BDCR1<2>), allows diagnostics to verify the BCI data path. When Force BCI Bad Parity is set, bad parity is forced on the BCI by the DWMBB/B module gate array. The BIIC logs the error and, if BIIC loopback mode is disabled, transmits the bad parity to the VAXBI, where it results in a bus error.
DWMBB Adapter 3.14.5 XMI Lockout Testing The DWMBB uses a software programmable limit of failed IREAD attempts before the XMI LOCKOUT L signal is asserted. Lockout Limit (AUTLR<31:28>), when set to zero, causes the DWMBB to assert the XMI LOCKOUT L signal after the first failed IREAD attempt. Table 3–22 lists the bits in ADG1 used to test the four lockout modes. It is necessary to clear ADG1<10> before clearing ADG1<30>. Table 3–22 Lockout Diagnostic Bits 3.14.
DWMBB Adapter 3.14.8 Diagnostic Read/Write Registers The DWMBB has two registers that act as temporary storage registers for diagnostics routines. They are readable/writable and can be used in loopback mode to verify the integrity of the main data paths. These registers follow: 3.14.
DWMBB Adapter 3.14.10 Error Conditions in Diagnostic Modes When diagnostics are being performed, error conditions, such as parity errors, ECC errors, and illegal DMA address errors, cause the DWMBB to fail. While the DWMBB is in BIIC or DMA loopback modes, the DWMBB handles forced and unforced errors the same as in normal mode. The error, failing command, and address information, if appropriate, are logged, and the appropriate error response is taken, if enabled.
4 Power and Cooling Systems The power system for the VAX 6000 platform consists of an AC power controller, the power and logic unit, three DC-to-DC power regulators (plus two optional power regulators for a VAXBI subsystem), an optional uninterruptible power supply, and a temperature sensor. The cooling system consists of two blower units and an airflow sensor, with the airflow path through the XMI and optional VAXBI card cages. See the VAX 6000 service manuals for more on power components. 4.
Power and Cooling Systems 4.1.1 Input Power The input power is five-wire (three-phase AC, neutral, and ground). 208V 60 Hz AC enters the H405-E AC power controller. 380V 50 Hz AC inputs the H405-F AC power controller and then enters the high-voltage autotransformer, which reduces the voltage to 208. The H405 AC power controllers suppress conducted emissions.
Power and Cooling Systems 4.1.3 H7214 Power Regulator The H7214 inputs 300V DC and +14V bias. A 30 kHz clock synchronizes this to all other power components. Outputs are 130 A of +5V DC and 0.5 A of +13.5V DC for Ethernet transceivers. A green LED on the regulator lights to indicate that the +5V output is present. 4.1.4 H7215 Power Regulator The H7215 inputs 300V DC and outputs 20 A of –5V DC, 7 A of –2V DC, 4 A of +12V DC, and 2.5 A of –12V DC.
Power and Cooling Systems 4.1.6.3 4–4 Console Line Driver and Receiver The XTC power sequencer contains the system console line driver and receiver, which are EIA RS-232/RS-423 compatible.
Power and Cooling Systems 4.1.7 Power System Signals Power system signals are partitioned so that a failure of one power supply shuts down only the XMI side and a failure of another power supply shuts down only the VAXBI side. The power system signals are described in Table 4–2. Table 4–2 Power System Signals Name Origin Destination Description PNL RESET L Control panel XTC Asserts when the control panel Restart button is pressed. Causes the XTC to start the reset sequence.
Power and Cooling Systems Table 4–2 (Cont.) Power System Signals 4.1.8 Name Origin Destination Description BBU Fail Safe Enable (BBU FSE L) H405/H7206-B BBU When asserted, the BBU may provide power to the system. When deasserted, the BBU is prevented from providing power. The signal is used during maintenance to prevent the application of BBU power. BATTERY BACKUP REQUEST H (BBUR H) H7206-B BBU Pulses and is asserted when AC OK deasserts, thus requesting the BBU to start supplying 300V DC.
Power and Cooling Systems • If the system has a VAXBI bus, the operating system stores all current VAXBI processes during the same 500 millisecond period. Power to the VAXBI card cage is then disabled. • The operating system stops. • The H7236-A continues to power the XMI card cage so memory is refreshed and data is held. If system power returns within 10 minutes, a warm restart is performed. The operating system continues from the point at which it stopped.
Index A ABEAR register • 3–94 See also VAXBI Error Address Register AC OK H signal • 4–5 AC power controller • 4–2 ACSR register Battery Backup Fail Safe Enable See BBU FSE L signal Battery Backup Request H See BBUR H signal Battery backup unit • 1–13, 1–15 BBUE H signal • 4–5 BBUE L signal • 4–5 BBU FSE L signal • 4–6 BBUR H signal • 4–6 BBU STATUS signal • 4–5 BCI AC LO bit • 3–61, 3–128 BCI AC LO L signal • 3–128 BCSR register See Control and Status Register (DWMBB/A module) Address Extension field •
Index BRSVD register • 3–111 BTIM register • 3–106 See also Timeout Address Register Bus Error Extension Register • 2–74 Bus Error Register • 2–58, 3–45 BVOR register See Vector Offset Register BVR register See Vector Register C Cable OK bit • 3–56, 3–129 Cache coherency • 2–52 Cacheing • 1–2 C/A Fetch Failed bit • 3–121, 3–122 CAFF bit See Command/Address Fetch Failed bit CC bit See Corrected Confirmation bit CCID bit See Corrected Confirmation Interrupt Disable bit CHANNEL n INHIBIT signal • 4–6 CHANNEL
Index DWMBB address translation (Cont.
Index Force Bad IBUS Receiver Parity bit • 3–79 Force Bad IBUS Transmit Parity bit • 3–79, 3–145 Force BCI Bad Parity bit • 3–110, 3–146 Force BIIC Loopback Mode bit • 3–110, 3–135 Force Data NO ACK bit • 3–75, 3–148 Force DMA-A Buffer Busy bit • 3–79, 3–140, 3–141, 3–142 FORCE DMA-A BUSY bit See Force DMA-A Buffer Busy bit Force DMA-B Buffer Busy bit • 3–79, 3–140, 3–141, 3–142 FORCE DMA-B BUSY bit See Force DMA-B Buffer Busy bit Force ECC Error bit • 3–77, 3–146 Force Illegal Command bit • 3–76, 3–148 Fo
Index Interrupt on I/O Write Fail bit • 3–127 Interrupt on I/O Write Failure bit • 3–69 Interrupt on IBUS DMA-A C/A Parity Error bit • 3–70 Interrupt on IBUS DMA-B C/A Parity Error bit • 3–70 Interrupt on IBUS I/O Read Data Parity Error bit • 3–71 Interrupt on Inconsistent Parity Error bit • 3–66 Interrupt on Internal Error bit • 3–69 Interrupt on Invalid PFN bit • 3–68, 3–116 Interrupt on Invalid VAXBI Address bit • 3–69, 3–116 Interrupt on No Read Response bit • 3–67 Interrupt on Parity Error bit • 3–66,
Index L N Latch Check Bits bit • 3–76, 3–146 LDEASRT field See Lockout Deassertion field LLIM See Lockout Limit field LOCKOUT ASSERT ENA bit See Lockout Assert Enable bit Lockout Assert Enable bit • 3–28, 3–88 Lockout Deassertion field • 3–30, 3–32, 3–82 Lockout Deassertion Timer field • 3–131 Lockout Limit field • 3–29, 3–81 Lockout Mode field • 2–71 Lockout modes • 3–28 to 3–32 LOCKOUT RESPONSE ENA bit See Lockout Response Enable bit Lockout Response Enable bit • 3–28, 3–88 LOCMOD field See Lockout Mod
Index PE bit See Parity Error bit PFN See Page frame number Platform differences • 1–2 PMR Correctable ECC Error bit • 3–118 PMRE See Page map register entry • 3–10 PMR Ready bit • 3–87, 3–128 PMR register See Page Map Register PMR Uncorrectable ECC Error bit • 3–118 PMR Valid bit • 3–96 PNL RESET L signal • 4–5 Power failure • 4–7 Power sequencer See XTC Programmable timeout • 3–34 R RCV LOCKOUT STATUS bit See Receive Lockout Status bit READ • 2–34 Read Error Response bit • 2–62, 3–30, 3–49, 3–124 Read/I
Index UNCORR DMA ECC ERR bit (Cont.
Index Write Data NO ACK bit • 2–62, 3–48, 3–124 Write error interrupt • 2–80 Write Error Interrupt bit • 2–60, 3–47 Write Error IVINTR • 2–80 Write Mask transaction • 2–38 Write Sequence Error bit • 2–61, 3–48, 3–124 Write transactions • 2–50 to 2–51 WSE bit See Write Sequence Error bit X XBAD bit See XMI BAD bit XBADD bit See XMI BAD Drive bit XBEER register See Bus Error Extension Register XBER register See Bus Error Register XBI INT PEND bit See DWMBB Interrupt-Pending Status bit XBI Power-Up LED bit X