Installation guide

1-20 Registers
Figure 1-36 VDATA — VIC Data Register
Figure 1-37 ICSR — Ibox Control and Status Register
Figure 1-38 BPCR — Ibox Branch Prediction Control Register
31 0
VIC_DATA
BXB-0134-92
31 43 05
0
12
00000000000000000000000000 0
BXB-0135-92
TPERR
DPERR
LOCK
VIC_ACC_ENB
31 16 15 9 43 08765
BPU_ALGORITHM 0 0 0 0 0 0 0 0
31 28 27 24 23 20 19 16 15 0
11111110110010100000000000000000
BXB-0136-92
As part of the power-up sequence, the microcode will write FECA0000, which is the following bit pattern:
LOAD_HISTORY
FLUSH_CTR
FLUSH_BHT
MISPREDICT
HISTORY
F E C A 0 0 0 0