User`s guide

System Initialization and Acceptance Testing (Normal Operation)
4.6 Main Memory Layout and State
4.6.3 Memory Controller Registers
The CPU firmware assigns bank numbers to the MEMCONn registers in
ascending order, without attempting to disable physical banks that contain
errors. High order unused banks are set to zero. Error loggers should capture
the following bits from each MEMCONn register:
• MEMCONn <31> (bank enable bit). As the firmware always assigns
banks in ascending order, knowing which banks are enabled is sufficient
information to derive the bank numbers.
• MEMCONn <2:0> (bank usage). This field determines the size of the banks
on the particular memory board.
Additional information should be captured from the NMCDSR, MOAMR,
MSER, and MEAR as needed.
4.6.4 On-Chip and Backup Caches
All three caches are tested.
4.6.5 Translation Buffer
The CPU translation buffer is tested by diagnostics on power-up, but not used
by the firmware because it runs in physical mode. The translation buffer can
be invalidated by using PR$_TBIA, IPR 57.
4.6.6 Halt-Protected Space
On the KA52/53/54, halt-protected space spans the first half of the 512K byte
FEPROM from 20040000 to 2007FFFF. The second half of the FEPROM has
data which is loaded into memory and run.
The firmware always runs in halt-protected space. When passing control to the
bootstrap, the firmware exits the halt-protected space, so if halts are enabled,
and the halt line is asserted, the processor will then halt before booting.
4.7 Operating System Bootstrap
Bootstrapping is the process by which an operating system loads and
assumes control of the system. The KA52/53/54 supports bootstrap of the
VAX/OpenVMS and VAXELN operating systems. Additionally, the KA52/53/54
will boot MDM diagnostics and any user application image which conforms to
the boot formats described herein.
On the KA52/53/54 a bootstrap occurs whenever a BOOT command is issued
at the console or whenever the processor halts and the conditions specified in
Table G–1 for automatic bootstrap are satisfied.
4–20 System Initialization and Acceptance Testing (Normal Operation)