User`s guide

KA52/53/54 CPU Module Description
1.4 Memory Tests
Test 4D - Address Uniqueness Test
The main purpose of the test is to verify that each set on each board can be
uniquely addressed. The test writes a unique pattern to each location to be
tested then verifies all locations.
Test 4C - MEMORY ECC, Verify Error Detection and Reporting
The main purpose of this test is to test ECC logic. It is not intended to test the
memory RAMs explicitly.
The test verifies that single and double bit errors are reported and logged
correctly in the MESR. It also verifies that single bit errors cause interrupts
through vector 54 when enabled and that double bit errors cause a machine
check.
In addition, the test also verifies that multiple bit errors can be detected using
data patterns that generate all of the syndrome values for multiple bit errors.
Test 4B - MEMORY Verify Masked Write Cycles with Errors
The test verifies operation of masked write cycles when the location contains
errors. In addition, it verifies that errors are reported and that single bit errors
are corrected.
Test 4A - MEMORY ECC, Verify Ability to Correct Single Bit Errors
This test verifies the correct operation of the error correction logic (ECC). It
does this by verifying that single bit errors can be detected and corrected in
any of the 64 data bits and that single bit errors are detected in the eight check
bits.
Test 48 - MEMORY Address/Shorts Test
This test verifies that all locations in each set can be uniquely written to and
that each of the 64 data bits in each QW can be written to a one and to a zero.
This test also writes all locations in memory with good ECC.
The test runs on a hexaword basis with all caches enabled to fully utilize
caching to speed up the test. Two primary data patterns of AAAAAAAA_
AAAAAAAA and 55555555_55555555 are used by the test. The ECC checkbits
for these patterns are complements of each other. By running this test, all data
and ECC bits in all locations in memory will be written as a 1 and a 0. The
test also detects addressing errors.
Test 47 - MEMORY Data Retention, Verify Refresh Logic
This test verifies that the refresh logic is working for all memory boards. The
test loads patterns into memory, waits a specified amount of time, then verifies
the patterns.
KA52/53/54 CPU Module Description 1–15