User`s guide

Configurable Machine State
31:24: CPU type - 13hex (NVAX code)
13:8: Patch revision
7:0: Microcode revision
ICSR: IBox Control and Status Register (IPR D3)
0: VIC enable
1 = enabled
ECR: EBox Control Register (IPR 7D)
13: FBox test enable
0 = disable* - diagnostic use only
7: Interval time mode
1 = full CPU implemented interval timer
5: S3 stall timeout
0 = counts cycles w/ timeout_enable asserted (~3 sec)*
3: FBox stage 4 bypass
1 = enabled - improves FBox latency
2: S3 external time base timeout
0 = disabled* - use internal time base
1: FBox enable
1 = enabled
0: Vector present
0 = no* - no vector option available at this time
MMAPEN: Memory Map Enable Register (IPR E6)
0: Memory map enable
0 = disabled* - OpenVMS enables this
PAMODE: Physical Address Mode Register (IPR E7)
0: Physical address mode
0 = 30-bit physical address space*
PCCTL: PCache Control Register (IPR F8)
8: PCache Electrical disable
0 = PCache enabled*
7:5 MBox performance monitor mode (0*) - diagnostic use
only
4: PCache error enable
1 = enables PCache error detection
3: Bank select during force hit mode
0 = left bank selected if force hit mode enabled*
- diagnostic use only
2: Force hit
0 = disabled* - diagnostic use only
1: I_enable
1 = enable PCache for IREAD, INVAL, I_CF commands
D–4 Configurable Machine State