User`s guide

Configurable Machine State
29: Diagnostic Checkbit mode
0 = disabled* - diagnostic use only
28: QBus on I01
0 = QBus on IO2*
27: Enable soft error log (NDAL & memory related)
0 = disabled* - OpenVMS enables this
26: Flush BCache
0 = don’t flush*
24:17: Memory diagnostic check bits (0*) - may not be read
as 0
8:7: NDAL Timeout Scaler
00 = 2600 cycles* - maximum to preserve timeout order
6: Disable memory error
0 = memory errors deteted and corrected*
5: Refresh interval timer select
0 = 328 cycles*
4:2: Force wrong parity on NDAL transactions - off
- diagnostic use only
1: Disable memory refresh
0 = memory refreshed*
0: Force refresh
0 = normal refresh*
NMC_CSR19: O-bit Address and Mode Register (2101 804C)
16: Ignore O-bit mode
0 = O-bits checked*
15: Disable O-bit error
0 = O-bit errors detected*
14:6: O-bit segment address (0*) - not used in normal
operation
5:3: O-bit mask (0*) - not used in normal operation
2:0: O-bit operation mode
X00 = reconstruction mode* - not used in normal
operation
NMC_OSCR: O-bit Data Registers (2101 0000 thru 2101 7FFF)
23:12: O-bit field 1 (0 at reset)
11:0: O-bit field 0 (0 at reset)
NVAX:
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CPUID: CPU ID Register (IPR E)
7:0: CPU identifcation = 0 (for single processor config.)
SID: System Identification Register (IPR 3E)
NOTE: this register may only be written by microcode
Configurable Machine State D–3