User`s guide

Conﬁgurable Machine State

The KA52/53/54 CPU modules have many control registers that need to be

conﬁgured for proper operation of the module. The following list shows the

normal state of all conﬁgurable bits in the CPU module as they are left after

the successful completion of power-up ROM diagnostics.

Configuration Register Bit Settings(* = reset state)

NCA:

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NCA_CSR1: Mode Control and Diagnostic Status Register (2102 0004)

15:14: CP2 MT Timer Prescaler

11 = 144000 cycles* - needed for CQBIC 10ms No Grant

timeout

13:12: CP1 MT Timer Prescaler

00 = 144 cycles - minimum for passive releases, no

cycle should take longer than this.

11:10: NDAL Timeout Prescaler

00 = 3200 cycles* - this is longer than both NCA and

NMC transactions timeouts, preserves timeout

order.

9: CQBIC mode

0 = CQBIC not present* - this is to avoid the

QBUS_TRANS deadlock.

Conﬁgurable Machine State D–1