User`s guide

Address Assignments
A.6 IPR Address Space Decoding
A.6 IPR Address Space Decoding
Table A–2 IPR Address Space Decoding
IPR Group Mnemonic
2
IPR Address Range
(hex) Contents
Normal 00000000..000000FF
1
256 individual IPRs.
Bcache Tag BCTAG 01000000..011FFFE0
1
64k Bcache tag IPRs, each separated
by 20(hex) from the previous one.
Bcache Deallocate BCFLUSH 01400000..015FFFE0
1
64k Bcache tag deallocate IPRs,
each separated by 20(hex) from the
previous one.
Pcache Tag PCTAG 01800000..01801FE0
1
256 Pcache tag IPRs, 128 for each
Pcache set, each separated by 20(hex)
from the previous one.
Pcache Data Parity PCDAP 01C00000..01C01FF8
1
1024 Pcache data parity IPRs, 512 for
each Pcache set, each separated by
8(hex) from the previous one.
1
Unused fields in the IPR addresses for these groups should be zero. Neither hardware nor microcode detects
and faults on an address in which these bits are nonzero. Although noncontiguous address ranges are shown
for these groups, the entire IPR address space maps into one of these groups. If these fields are nonzero, the
operation of the CPU is UNDEFINED.
2
The mnemonic is for the first IPR in the block.
Processor registers in all groups except the normal group are processed entirely
by the NVAX CPU chip and will never appear on the NDAL. This is also true
for a number of the IPRs in the normal group. IPRs in the normal group
that are not processed by the NVAX CPU chip are converted into I/O space
references and passed to the system environment via a read or write command
on the NDAL.
Each of the 256 possible IPRs in the normal group are of longword length, so
a 1-KB block of I/O space is required to convert each possible IPR to a unique
I/O space longword. This block starts at address E1000000 (hex). Conversion
of an IPR address to an I/O space address in this block is done by shifting the
IPR address left into bits <9:2>, filling bits <1:0> with zeros, and merging in
the base address of the block. This can be expressed by the equation:
Address Assignments A–21