User`s guide

Address Assignments
A.5 Processor Registers
Table A–1 (Cont.) Processor Registers
Number
Register
Name Mnemonic (Dec) (Hex) Type Impl Cat
I/O
Address
See
Table A–2
01000000–
FFFFFFFF
2
Type:
R = Read-only register
RW = Read-write register
W = Write-only register
Impl(emented):
NVAX = Implemented in the NVAX CPU chip
System = Implemented in the system environment
Vector = Implemented in the optional vector unit or its NDAL interface
Cat(egory), class-subclass, where:
class is one of:
1 = Implemented as per DEC standard 032
2 = NVAX-specific implementation which is unique or different from the DEC standard 032 implementation
3 = Not implemented internally; converted to I/O space read or write and passed to system environment
subclass is one of:
1 = Processed as appropriate by Ebox microcode
2 = Converted to Mbox IPR number and processed via internal IPR command
3 = Processed by internal IPR command, then converted to I/O space read or write and passed to system
environment
4 = If virtual machine option is implemented, processed as in 1, otherwise as in 3
5 = Processed by internal IPR command
6 = May be block decoded; reference causes UNDEFINED behavior
7 = Full interval timer may be implemented in the system environment. Subset ICCS is implemented in
NVAX CPU chip
8 = Converted to MFVP MSYNC
A–20 Address Assignments