User`s guide

Address Assignments
A.5 Processor Registers
Table A–1 (Cont.) Processor Registers
Number
Register
Name Mnemonic (Dec) (Hex) Type Impl Cat
I/O
Address
Memory
Management
Enable
1 2
MAPEN 56 38 RW NVAX 1-2
Translation
Buffer
Invalidate
All
2
TBIA 57 39 W NVAX 1-1
Translation
Buffer
Invalidate
Single
2
TBIS 58 3A W NVAX 1-1
Reserved 59 3B 3 E10000EC
Reserved 60 3C 3 E10000F0
System
Identification
SID 62 3E R NVAX 1-1
Translation
Buffer
Check
TBCHK 63 3F W NVAX 1-1
IPL 14
Interrupt
ACK
3
IAK14 64 40 R SSC 2-3 E1000100
IPL 15
Interrupt
ACK
3
IAK15 65 41 R SSC 2-3 E1000104
IPL 16
Interrupt
ACK
3
IAK16 66 42 R SSC 2-3 E1000108
IPL 17
Interrupt
ACK
3
IAK17 67 43 R SSC 2-3 E100010C
Clear Write
Buffer
3
CWB 68 44 RW SSC 2-3 E1000110
1
Initialized on reset
2
Change broadcast to vector unit if present
3
Testability and diagnostic use only; not for software use in normal operation
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Address Assignments A–13