User`s guide

Address Assignments
A.2 KA52/53/54 Detailed Local Address Space Map
KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.)
Local Register I/O Space (Cont.)
Timer 0 Control Register 2014 0100
Timer 0 Interval Register 2014 0104
Timer 0 Next Interval Register 2014 0108
Timer 0 Interrupt Vector 2014 010C
Timer 1 Control Register 2014 0110
Timer 1 Interval Register 2014 0114
Timer 1 Next Interval Register 2014 0118
Timer 1 Interrupt Vector 2014 011C
Reserved Local Register I/O Space 2014 0120 - 2014 012F
BDR Address Decode Match Register 2014 0140
BDR Address Decode Mask Register 2014 0144
Reserved Local Register I/O Space 2014 0138 - 2014 03FF
Battery Backed-Up RAM 2014 0400 - 2014 07FF
Reserved Local Register I/O Space 2014 0800 - 201F FFFF
Reserved Local I/O Space 2020 0000 - 2FFF FFFF
Local Q22-bus Memory Space 3000 0000 - 303F FFFF
Reserved Local Register I/O Space 3040 0000 - 3FFF FFFF
A.3 External, Internal Processor Registers
Several of the Internal Processor Registers (IPR’s) on the KA52/53/54 are
implemented in the NCA or SSC chip rather than the CPU chip. These
registers are referred to as External Internal Processor Registers and are listed
below.
IPR # Register Name Abbrev.
===== ============= ======
27 Time of Year Register TOY
28 Console Storage Receiver Status CSRS*
29 Console Storage Receiver Data CSRD*
30 Console Storage Transmitter Status CSTS*
31 Console Storage Transmitter Data CSDB*
32 Console Receiver Control/Status RXCS
33 Console Receiver Data Buffer RXDB
34 Console Transmitter Control/Status TXCS
35 Console Transmitter Data Buffer TXDB
55 I/O System Reset Register IORESET
* These registers are not fully implemented, accesses yield
UNPREDICTABLE results.
A–8 Address Assignments