User`s guide

KA52/53/54 CPU Module Description

1.1 KA52/53/54 CPU Module

• DC541 SGEC chip Ethernet controller for standard or ThinWire Ethernet

• DC7085 (QUART) serial line controller (4 serial lines, one with modem

control)

• 128K bytes (KA52) or 512K bytes (KA53/54) of second level write-back

cache memory

• Basic system memory (16M bytes of random-access memory (RAM)

consisting of four MS44L-AA memory modules or 64M bytes of RAM

consisting of four MS44-CA )

• Support for up to 128M bytes of RAM

• 512K bytes of read-only memory (ROM)—This ROM contains the boot

and diagnostic ﬁrmware for the system.

• 32-byte network address ROM

• Four asynchronous communications ports as follows:

Three DEC423 ports—These ports are modiﬁed modular jack (MMJ)

connectors.

One modem control port—This port is a D-sub 25-way connector.

• Provision for asynchronous communications options that provide one of the

following:

Eight or 16 additional DEC423 ports

Eight additional modem ports

• Provision for synchronous communications options that provide:

Two synchronous ports

1.1.2 Functional Description

Figure 1–2 is a block diagram of the KA53/54 CPU module. The KA52 (not

shown) has 128 Kbytes of cache instead of 512, but is otherwise identical.

KA52/53/54 CPU Module Description 1–3