User`s guide

System Troubleshooting and Diagnostics
5.1 Basic Troubleshooting Flow
If you change the system configuration, run the CONFIGURE utility at the
console I/O prompt (>>>) to determine the CSR addresses and interrupt vectors
recommended by Digital. These recommended values simplify the use of the
MDM diagnostic package and are compatible with OpenVMS device drivers.
You can select nonstandard addresses, but they require a special setup for use
with OpenVMS drivers and MDM. See the MicroVAX Diagnostic Monitor User’s
Guide for information about the CONNECT and IGNORE commands, which
are used to set up MDM for testing nonstandard configurations.
5.2 Product Fault Management and Symptom-Directed
Diagnosis
This section describes how errors are handled by the microcode and software,
how the errors are logged, and how, through the Symptom-Directed Diagnosis
(SDD) tool, VAXsimPLUS, errors are brought to the attention of the user. This
section also provides the service theory used to interpret error logs to isolate
the FRU. Interpreting error logs to isolate the FRU is the primary method of
diagnosis.
5.2.1 General Exception and Interrupt Handling
This section describes the first step of error notification: the errors are first
handled by the microcode and then are dispatched to the OpenVMS error
handler.
The kernel uses the NVAX core chipset: NVAX CPU, NVAX Memory Controller
(NMC), and NDAL to CDAL adapter (NCA).
Internal errors within the NVAX CPU result in machine check exceptions,
through System Control Block (SCB) vector 004, or soft error interrupts at
Interrupt Priority Level (IPL) 1A, SCB vector 054 hex.
External errors to the NVAX CPU, which are detected by the NMC or NDAL to
CDAL adapter (NCA), usually result in these chips posting an error condition
to the NVAX CPU. The NVAX CPU will then generate a machine check
exception through SCB vector 004, hard error interrupt, IPL 1D, through SCB
vector 060 (hex), or a soft error interrupt through SCB vector 054.
External errors to the NMC and NCA, which are detected by chips on the
CDAL busses for transactions which originated by the NVAX CPU, are
typically signaled back to the NCA adapter. The NCA adapter will post an
error signal back to the NVAX CPU which generates a machine check or high
level interrupt.
System Troubleshooting and Diagnostics 5–3