Service manual

The CPU section includes:
• The CVAX processor chip, which supports the VAX Base Instruction
Group and data types. It has full VAX memory management including
demand paging and 4 Gbytes of virtual memory. The CPU chip includes
the first-level cache, for I-stream (instruction) storage only. First-level
cache is 1 Kbyte, organized with 128 tags. Cache is write-through,
two-way associative, and is filled eight bytes at a time.
• A floating-point accelerator chip, which supports the VAX Base
Instruction Group floating-point instruction set. Data types supported
by the hardware are D_floating, F_floating, and G_floating.
• The clock chip includes a VAX standard time-of-year (TOY) clock with
access to battery backup, an interval timer with 10 ms interrupts, and
two programmable timers.
The second-level cache is for both I-stream and D-stream (data) storage.
Second-level cache is 256 Kbytes, organized with 4096 tags. Cache is write-
through and direct-mapped. If a processor read misses an entry in the
cache, or if the entry is invalid, the XMI gate array reads the data from
main memory. Cache is filled 32 bytes at a time; the first longword read
satisfies the processor’s read request.
The <REFERENCE>(XMI) interface includes:
• An octaword write buffer that decreases bus and memory controller
bandwidth needs by packing writes into larger, more efficient blocks
prior to sending them to main memory.
• Hexword cache fill logic that loads the second-level cache with eight
longwords of data on each cache miss.
• <REFERENCE>(XMI) write monitoring logic that uses a duplicate
tag store to detect when another <REFERENCE>(XMI) node writes a
memory location that is cached on this processor. Then the gate array
invalidates the corresponding entry in the second-level cache.
• Full set of error recovery and logging capabilities.
<REFERENCE>(xyp) Scalar Processor 3–7