Service manual

6.13 MS65A Control and Status Registers
The memory contains 19 control and status registers (CSRs)
to control the memory and log errors. All CSRs are 32
bits long and respond only to longword read and write
transactions. Only full writes are performed to the CSRs. If
a parity error occurs during a write operation, the operation
is aborted and the contents of the CSRs are unchanged.
The CSRs start at an address dependent upon the node ID. All CSR
addresses are designated as BB + n, where n is the relative offset of the
register.
Table 6–5: <REFERENCE>(xma2) Control and Status Regis-
ters
.
CSR Name Mnemonic Address
Device Type Register XDEV BB
1
+ 00
Bus Error Register XBER BB + 04
Starting and Ending Address Register SEADR BB + 10
Memory Control Register 1 MCTL1 BB + 14
Memory ECC Error Register MECER BB + 18
Memory ECC Address Register MECEA BB + 1C
Memory Control Register 2 MCTL2 BB + 30
TCY Tester Register TCY BB + 34
Block State ECC Error Register BECER BB + 38
Block State ECC Address Register BECEA BB + 3C
Starting Address Register STADR BB + 50
Ending Address Register ENADR BB + 54
Segment/Interleave Control Register INTLV BB + 58
Memory Control Register 3 MCTL3 BB + 5C
Memory Control Register 4 MCTL4 BB + 60
1
"BB" refers to the base address of an <REFERENCE>(XMI) node (2180 0000 + (node ID x
8000))
6–24 VAX 6000 Models 300 and 400 Service Manual