Service manual

The <REFERENCE>(xrv) is an integrated vector processor, tightly coupled
to the <REFERENCE>(XRP) scalar processor. The vector instructions are
issued from the scalar processor, and the vector processor then dispatches
them internally. All communication between the scalar and vector modules
takes place across the intermodule VIB cable. All communication with
memory is over the XMI bus.
The vector processor has 16 vector data registers, each 64 quadwords long.
There is a 1-megabyte direct-mapped cache and a 136-entry translation
buffer.
The <REFERENCE>(xrv) is an XMI module with the standard XMI
Corner. The module has a cable connector at the rear edge of the module
that connects to the rear edge of a <REFERENCE>(XRP) module. The
instructions are issued over the VIB bus and pass to the VECTL chip,
which then controls the operations on the module. It passes instructions
to the load/store unit over the CD bus. The load/store unit then issues
XMI memory transactions. The VECTL chip also issues instructions to the
four pairs of Verse and Favor chips that make up the arithmetic unit. The
vector data registers are in the Verse chips. The Favor chips perform the
arithmetic operations on the data held in the Verse chips.
The vector processor module uses the standard XMI Corner interface, but it
functions only as an XMI commander. The vector processor does not issue
transactions to I/O space, nor does it respond to XMI transactions directed
to it. All error reporting is done by the scalar processor.
<REFERENCE>(XRV) Vector Processor 5–9