Service manual

4.19 <REFERENCE>(XRP) Registers

The <REFERENCE>(XRP) registers consist of the proces-

sor status longword, internal processor registers, <REFER-

ENCE>(XRP) registers in <REFERENCE>(XMI) private space,

<REFERENCE>(XMI) required registers, and 16 general pur-

pose registers.

Table 4–11: <REFERENCE>(XRP) Internal Processor Registers

Kernel Stack Pointer KSP IPR0 R/W 1

Executive Stack Pointer ESP IPR1 R/W 1

Supervisor Stack Pointer SSP IPR2 R/W 1

User Stack Pointer USP IPR3 R/W 1

Interrupt Stack Pointer ISP IPR4 R/W 1

Reserved IPR5–IPR7 3

P0 Base P0BR IPR8 R/W 1

P0 Length P0LR IPR9 R/W 1

P1 Base P1BR IPR10 R/W 1

P1 Length P1LR IPR11 R/W 1

Key to Types:

R–Read

W–Write

R/W–Read/write

Key to Classes:

1–Implemented by the <REFERENCE>(XRP) (as speciﬁed in the VAX Architecture Refer-

ence Manual).

2–Implemented uniquely by the <REFERENCE>(XRP).

3–Not implemented. Read as zero; NOP on write.

4–Access not allowed; accesses result in a reserved operand fault.

5–Accessible, but not fully implemented; accesses yield UNPREDICTABLE results.

6–Implemented by the FV64A vector module.

I–The register is initialized on <REFERENCE>(XRP) reset (power-up, system re-

set, and node reset).

4–60 VAX 6000 Models 300 and 400 Service Manual