Service manual

The CPU section includes:
• The processor chip, which supports the VAX Base Instruction Group
and data types. It contains a 64-entry, fully associative translation
buffer for both process and system-space mappings. The processor chip
includes a 2-Kbyte, direct-mapped, write-through instruction and data
cache with a quadword block and fill size.
• A floating-point accelerator chip that enhances the computation phase
of floating-point and some integer instructions. This chip receives
operands from the processor chip, computes the result, and passes the
result and status back to the processor chip to complete the instruction.
The backup cache is a 128-Kbyte, direct-mapped, write-through instruction
and data cache. It is implemented in 24 16-Kbyte x 4 data RAMs. The
backup cache contains 2-Kbyte tags, organized to provide an octaword fill
size and a 4-octaword block size.
The <REFERENCE>(XMI) interface includes:
• An octaword write buffer that decreases bus and memory controller
bandwidth needs by packing writes into larger, more efficient blocks
prior to sending them to main memory.
• Cache fill logic that loads the backup cache with four octawords of data
on each cache miss.
• <REFERENCE>(XMI) write monitoring logic that uses a duplicate
tag store to detect when another <REFERENCE>(XMI) node writes
a memory location that is cached on this processor. Then the XMI
interface chips invalidate the corresponding entry in the backup cache.
• Full set of error recovery and logging capabilities.
<REFERENCE>(XRP) Scalar Processor 4–7