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• The address range shall be naturally aligned. Which means that the addr shall be
aligned to a boundary that is multiple of the len. Or more formally:
(addr + (len - 1)) == (addr | (len - 1))
The procedure is invoked as follows:
io_space_id_t sid = …;
const chapi_in * ci = …;
if (ci->connect_io_space) {
ci->connect_io_space(ci, sid, addr, len);
}
The example above shows that the CHARON core is not obliged to support the indicated
operation. Also, it gives a clue why the device instance is supposed to remember the I/O
space identifier returned in the previous call to create_io_space procedure (see above), and
the chapi_in descriptor.
4.8 The legacy way to process interrupts
The operations described in this section are only listed for compatibility reasons
with a prior implementation of CHAPI. While these methods are supported in the
current release, they should not be used in a new development using CHAPI. See
the next section for the recommended methods.
4.8.1 Requesting a bus interrupt
The operation of requesting a bus interrupt belongs to the group of operations previously
called “Request for bus interrupt”. Such an operation is initiated by the device instance
when it is in execution context synchronized to the CPU instruction interpretation thread.
The CHARON core is defined as the target of the operation. Actually the CPU instruction
interpretation thread is supposed to respond to the bus interrupt request.
In order to perform the operation, the initiator invokes a routine identified by the put_irq
field of the chapi_in descriptor. The procedure is invoked as follows:
const chapi_in * ci = …;
if (ci->put_irq) {
ci->put_irq(ci, vec, delay, fun, arg1, arg2);
}
The example above shows that the CHARON core is not obliged to support the indicated
operation. It also indicates why the device instance should remember the chapi_in
descriptor.
4.8.2 Removing a bus interrupt request
Removing a bus interrupt request belongs to the “Request for bus interrupt” group of
operations. Such an operation is initiated by the device instance when it is in execution
context synchronized to the CPU instruction interpretation thread. The CHARON core is