Specifications

14 EISA and ISA Bus Support
14.1 Evolution of the EISA Bus ..................................... 14–1
14.2 Intel 82350DT EISA Chipset . . . ................................ 14–2
14.3 EISA Bus Resources. . ........................................ 14–2
14.3.1 IRQs. . . ................................................ 14–2
14.3.2 DMA Channel . . . ........................................ 14–2
14.3.3 I/O Port Addresses ........................................ 14–3
14.3.4 EISA Memory Addresses . . . ................................ 14–3
14.3.5 EISA Configuration Utility . ................................ 14–3
14.4 EISA Interrupts ............................................. 14–4
14.5 EISA DMA Support . . ........................................ 14–4
14.6 EISA I/O Address Map........................................ 14–5
14.7 EISA Bus Support on DEC 2000 ................................ 14–6
14.7.1 DEC 2000 System Address Map ............................. 14–6
14.7.1.1 DEC 2000 Address Space ................................ 14–7
14.7.1.2 DEC 2000 System Memory (0-FFF.FFFF) ................... 14–7
14.7.1.3 INTA Cycle Access (1.0000.0000) . . . ....................... 14–8
14.7.1.4 NVRAM Access (1.8000.0000, 1.A000.0000) . . . ............... 14–8
14.7.1.5 VTI VL82C106 Combination Chip (1.C000.0000) .............. 14–8
14.7.1.6 Host Address Extension Register (1.D000.0000) .............. 14–8
14.7.1.7 System Control Register Access ( 1.E000.0000) ............... 14–9
14.7.1.8 EISA Memory Space Access (2.0000.0000 - 2.FFFF.FFFF) ....... 14–9
14.7.1.9 EISA I/O Space Access (3.0000.0000 - 3.FFFF.FFFF)........... 14–11
14.7.2 Sparse Space ............................................ 14–13
14.7.3 Register Access . . ........................................ 14–14
14.7.3.1 Direct Register Access . . ................................ 14–14
14.7.3.2 CRAM Register Access . . ................................ 14–14
14.7.4 DMA on DEC 2000 ....................................... 14–15
14.7.4.1 DMA Example ........................................ 14–15
14.7.5 I/O Interrupts on DEC 2000. ................................ 14–16
14.7.5.1 EISA IRQs . . . ........................................ 14–16
14.7.5.2 SCB Vectors . . ........................................ 14–17
14.7.5.3 EOI ................................................ 14–17
14.7.6 EISA Bus Interface Registers................................ 14–17
14.7.6.1 Interrupt Enable Register ............................... 14–17
14.7.6.2 End of Interrupt Command .............................. 14–17
14.7.6.3 IOC$NODE_FUNCTION and IOC$NODE_DATA ............. 14–17
14.7.6.3.1 IOC$NODE_FUNCTION ............................. 14–17
14.7.6.3.2 IOC$NODE_DATA . . ................................ 14–18
14.7.6.3.3 CRB$L_NODE ..................................... 14–19
14.7.7 DEC 2000 I/O Space Map . . ................................ 14–19
14.7.8 Configuring a Device on DEC 2000 ........................... 14–20
14.7.8.1 Vector parameter ...................................... 14–21
14.7.8.2 Node parameter ....................................... 14–21
14.7.8.3 CSR parameter ....................................... 14–21
14.7.8.4 Resource Assignment on DEC 2000 . ....................... 14–21
14.7.8.4.1 IRQ’s ............................................ 14–21
14.7.8.4.2 EISA Memory Addresses ............................. 14–22
14.7.8.4.3 ISA I/O Port Addresses .............................. 14–22
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