Specifications

2
Accessing Device Interface Registers
A hardware interface register is the place where software interfaces with a
hardware component. Every hardware component on an OpenVMS AXP system,
including CPU and memory, has a set of interface registers.
The portion of a processor’s physical address space through which it accesses
hardware interface registers is known as its I/O space.
In the VAX architecture, a hardware implementation usually defines a physical
address boundary between memory space and I/O space. I/O space physical
addresses are mapped into the processors’ virtual address space and are accessed
using VAX load and store instructions (for example, MOV, BIS, and others).
For AXP systems, there are no rules governing how hardware implementations
allow access to I/O space. Some AXP platforms allow VAX-style I/O space access.
Other platforms provide access to I/O space through hardware I/O mailboxes.
Some platforms implement both styles of I/O register access.
The challenge presented by the AXP architecture is to create software
abstractions that hide the hardware mechanisms for I/O space access from the
programmer. These software abstractions contribute to driver portability. The
AXP architecture also defines no byte or word length load and store instructions.
Because some I/O buses and adapters require byte or word register access
granularity for correct adapter operation, AXP system hardware designers
invented the following mechanisms that provide byte and word access granularity
for I/O adapter register access:
• Sparse space addressing, which means the device address space is
expanded by a factor of two to allow for inclusion of a byte mask in the write
data.
• Swizzle space addressing, which means where upper order bits in the
processor physical address map to an I/O bus address, while lower order
bits are used to implement I/O bus byte enable signals. This causes a large
amount of processor physical address space to represent the I/O bus address
space.
• Hardware I/O mailboxes, which are 64-byte, naturally-aligned, physically-
contiguous data structures (defined by the AXP architecture) built in system
memory and accessed by special I/O subsystem hardware. Drivers can use
hardware I/O mailboxes to deliver commands and write data to the interface
registers of a device residing on an I/O bus.
A significant part of I/O bus support in the OpenVMS AXP operating system is
to provide standard ways to access I/O device registers. OpenVMS AXP provides
a set of data structures and routines that can be used for register access on any
system, regardless of the underlying I/O hardware. Bus support provides two
ways. One way is the CRAM data structure. The other way is the platform
independent access routines IOC$READ_IO and IOC$WRITE_IO.
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