Specifications

Introduction
1.6 Programmed-I/O and Direct-Memory-Access Transfers
1.6.1 Programmed I/O
Drivers for relatively slow devices, such as printers, terminals, and some disk and
tape drives, must transfer data to a hardware interface register a byte or a word
at a time. These drivers must themselves keep a record of the location of the data
buffer in memory, as well as a running count of the amount of data that has been
transferred to or from the device. Thus, these devices perform programmed I/O
(PIO) in that the transfer is largely conducted by the driver program.
The DE422 ISA ethernet interface is an example of a device that uses
programmed I/O.
Drivers performing PIO transfers are generally not concerned with the operation
of I/O adapters. However, drivers that perform direct-memory-access (DMA)
transfers must consider I/O adapter functions, as discussed in Section 1.6.2.
1.6.2 Direct-Memory-Access I/O
Devices that perform direct-memory-access (DMA) transfers do not require
the central processor so frequently. Once the driver activates the device, the
device can transfer a large amount of data without requesting an interrupt after
each of the smaller amounts. The responsibilities of a driver for a DMA device
involve setting a hardware interface register with the starting address of the
buffer containing the data to be transferred, a byte offset into the buffer, and
the size of the transfer. By setting the appropriate bit or bits in the hardware
interface control and status register (CSR), the driver activates the device. The
device then automatically transfers the specified amount of data to or from the
specified address. Any driver that does DMA must map the DMA buffer. For
DMA transfers, drivers must first map the transfer from main memory to I/O
bus memory space. The result of this mapping is a set of contiguous addresses in
the bus address space that the DMA device can access to successfully perform a
DMA transfer. If the bus interface does not have map registers, a bus address is
equivalent to a main memory address. If the bus interface has map registers, a
bus address undergoes a translation before becomming a system memory address.
1.7 Buffered and Direct I/O
A separate issue, but one related to the data transfer capabilities of a device,
results from the fact that the original buffer, as specified in the user $QIO
request, is in process space and is mapped by process page-table entries. Because
the driver cannot rely on process context existing at the time the device is ready
to service the I/O request, it must have some means of guaranteeing that it can
access both the data involved in the transfer and the page-table entries that map
the buffer.
The operating system provides the following two techniques that are employed by
device drivers:
• Direct I/O, the technique used most commonly by drivers of DMA devices,
locks the user buffer in memory as well as the page-table entries that map
it. The function decision table (FDT) of such a driver calls a system-supplied
FDT routine that prepares the user buffer for direct I/O.
• Buffered I/O is the strategy whereby the driver FDT dispatches to an FDT
routine in the driver that allocates a buffer from nonpaged pool. It is this
intermediate buffer that is involved in the transfer. The driver later refers
to the buffer using addresses in system space. Driver preprocessing routines
copy the data from the user buffer to the system buffer for a write request;
system I/O postprocessing (by means of a special kernel-mode AST) delivers
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