Specifications

5/9/13 888-2857-001 6-7
WARNING: Disconnect primary power prior to servicing.
Section 6 Diagnostics
Platinum VAX-C Series
Modulator Input D Indicates input D
is present in MOD
FPGA. ATSC
SMPTE B
System LED red.
TS Input LED
yellow or red.
MPEG sync
indicator = 1
MPEG sync indicator = 0
AND
input D selected for primary or
auxiliary input
Modulator Input Signal
Loss
Indicates required
inputs are not
present in MOD
FPGA.
System and Mute
LEDs red.
Depends on
modulation
standard. Relevant
inputs present.
DVB-T:
SFN mode AND hierarchy :
Auto switch mode: HP or LP bad on
both ASI 1 and ASI 2,
Manual switch mode: HP or LP bad
on selected input,
SFN mode AND non-hierarchy:
Auto switch mode: HP bad on both
inputs,
Manual switch mode: HP bad on
selected input
Modulation Mute Indicates
modulator FPGA
has muted
System and Mute
LEDs red.
Depends on
modulation
standard.
Modulator not
muted, other
conditions ok
DVB-T:
Mute bit set in MOD FPGA
ASI1 HP Rate
Overflow/Underflow
Indicates overflow
or underflow on
ASI 1 HP in MOD
FPGA for DVB
System LED red (overflow bit in
DDR1. Reg 15 bit
15 = 0) AND
(underflow bit in
DDR1. Reg 15 bit
13 = 0)
(overflow bit in DDR1. Reg 15 bit
15 = 1) OR (underflow bit in DDR1.
Reg 15 bit 13 = 1)
ASI1 LP Rate
Overflow/Underflow
Indicates overflow
or underflow on
ASI 1 LP in MOD
FPGA for DVB
System LED red (overflow bit in
DDR1. Reg 15 bit
14 = 0) AND
(underflow bit in
DDR1. Reg 15 bit
12 = 0)
Hierarchy mode, (overflow bit in
DDR1. Reg 15 bit 14 = 1) OR
(underflow bit in DDR1. Reg 15 bit
12 = 1)
ASI2 HP Rate
Overflow/Underflow
Indicates overflow
or underflow on
ASI 2 HP in MOD
FPGA for DVB
System LED red (overflow bit in
DDR2. Reg 15 bit
11 = 0) AND
(underflow bit in
DDR1. Reg 15 bit
9 = 0)
(overflow bit in DDR2. Reg 15 bit
11 = 1) OR (underflow bit in DDR2.
Reg 15 bit 9 = 1)
ASI2 LP Rate
Overflow/Underflow
Indicates overflow
or underflow on
ASI 2 LP in MOD
FPGA for DVB
System LED red (overflow bit in
DDR2. Reg 15 bit
10 = 0) AND
(underflow bit in
DDR1. Reg 15 bit
8 = 0)
Hierarchy mode, (overflow bit in
DDR2. Reg 15 bit 10 = 1) OR
(underflow bit in DDR2. Reg 15 bit
8 = 1)
DAB (modulation specific)
Table 6-3 MODFPGA Modulation Specific Faults
Fault Log Message Fault Description Front Panel LEDs
Nominal Value/
Scaling
Trip Level