Instruction manual

5.2 Organization

Each entry’s format and contents are:

04 03 0021 2023 22

MR−0079−93RAGS

V F P PPN UNP

Bits Description

3:0 UNPREDICTABLE. Unused and ignored in the parity calculation.

20:4 Physical page number. Translation of the virtual index: 17 bits.

21 Parity bit. Odd parity bit for the entire entry.

22 Funny bit. When set to 1, forces bad parity into the scatter/gather map for

diagnostic purposes.

23 Valid bit. When set, entry is valid

In Figure 8 a 34-bit virtual DMA byte address received from the TURBOchannel

is transformed using the scatter/gather map into a 30-bit physical DMA byte

address.

Figure 8 DMA byte address from TURBOchannel

0013 1228 2733

0013 1229

MR−0080−93RAGS

DISCARDED VIRTUAL PAGE BYTE WITHIN PAGE

BIT

BUCKET

SCATTER/GATHER MAP

PPN<16:0>

PPN BYTE WITHIN PAGE

PHYSICAL DMA BYTE ADDRESS (SENT TO MEMORY SYSTEM)

The scatter/gather map is indexed with virtual DMA byte address <27:13>. The

read PPN is appended with virtual DMA byte address <12:0> to give a 30-bit

physical DMA byte address. This 30-bit address can reference the maximum

possible memory space.

The term virtual DMA byte address is used for the purpose of explanation, although the

TURBOchannel supports longword addresses.

5–2 Scatter/Gather (Virtual DMA) RAMs (400/500/600/700/800/900 Models)