Instruction manual
5
Scatter/Gather (Virtual DMA) RAMs
(400/500/600/700/800/900 Models)
Scatter/gather registers in the DEC 3000 (400/500/600/700/800/900 models) carry
out an address translation scheme to implement virtual DMA.
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This chapter covers the following topics:
• Scatter/gather register map (Section 5.1)
• Organization (Section 5.2)
• Writing and reading scatter/gather map entries (Section 5.3)
5.1 Scatter/Gather Register Map
The scatter/gather register’s addresses, size, and access modes:
Table 13 Scatter/Gather Registers
Start Address End Address Size Access Mode
1.C280.0000 (dense space) 1.C281.FFFF 128 KB R
1.D500.0000 (sparse space) 1.D503.FFFF 256 KB R/W
Note
Reading either dense space 1.C280.0000 to 1.2C81.FFFF or sparse space
1.D500.0000 to 1.D503.FFFF reads the scatter/gather Map.
Writing to sparse space 1.D500.0000 to 1.D503.FFFF modifies the scatter
/gather map.
Writing to the scatter/gather RAMs in dense space (address range
1C280.0000 to 1C281.FFFF) modifies the interrupt mask register.
The scatter/gather RAMs contain 32K entries, each of which is 24 bits wide,
although some bits are unused. Each entry is addressable through a longword in
this I/O space. Entries may be read in either dense or sparse I/O space, but can
only be written to in sparse space.
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The term ‘‘scatter/gather’’ may also be used to signify a DMA transfer list, each of whose
elements contains a DMA address and the number of dta items to transfer. This is not
the meaning intended in the following sections.
Scatter/Gather (Virtual DMA) RAMs (400/500/600/700/800/900 Models) 5–1