Instruction manual

Note
Bits below <23> and above <29> need never be compared: the smallest
bank is 8 MB and the 500/500S/800/900 models are limited to 1 GB
maximum memory.
• Mask half (address bits <26:23>
The bank size determines the mask bit:
Bank Size Mask<26:23>
8 MB 0000
32 MB 0011
128 MB 1111
4.1.2 Boot Time
At boot time, the console must assume that all banks are of the largest possible
size (128 MB). It writes the MCRs with that assumption and then performs write
and read operations to memory space to see whether the specified amount of
memory is really there. If there is no memory in a bank, the data read does not
compare with the data written. If there is memory in the bank, but its size is less
than 128 MB, the write wraps within the memory bank.
Note
Due to bus access speed and capacitance, after you perform a write
operation on the test location, perform a read or write operation on
another location before returning to read the contents of the test location.
The following table lists how to write MCRs, assuming the largest possible
memory size:
MCR#
Bank
Size Compare<29:23> Mask<26:23> Address Space
0 128 MB 000xxxx 1111 000 - 127 MB
1 128 MB 001xxxx 1111 128 - 255 MB
2 128 MB 010xxxx 1111 256 - 383 MB
3 128 MB 011xxxx 1111 384 - 511 MB
4 128 MB 100xxxx 1111 512 - 639 MB, 500/500S/800
/900 models
5 128 MB 101xxxx 1111 640 - 767 MB, 500/500S/800
/900 models
6 128 MB 110xxxx 1111 768 - 895 MB, 500/500S/800
/900 models
7 128 MB 111xxxx 1111 896 - 1000 MB, 500/500S/800
/900 models
Address ASIC Registers (400/500/600/700/800/900 Models) 4–3