Instruction manual

3.3.5 Memory Configuration Registers
Memory configuration registers are described in Section 4.1.
3.3.6 Interrupt Mask Register (IMR)—1.C240.0000
The interrupt mask register holds copies of the reasons for machine check
interrupts and the mask for I/O interrupts.
Note
Reading dense space 1.C240.0000 reads the interrupt mask register.
Reading the corresponding sparse space 1.D480.0000 reads the interrupt
register.
Reading the interrupt mask register at address 1.C260.0000 clears the
interrupt register. This should not be done. Read address 1.D4C0.0000 to
clear the interrupt register.
Writing to dense space 1.C280.0000 to 1.2C81.FFFF modifies the interrupt
mask register; by convention, 1.C281.FFFC is used as the address of the
interrupt mask register. Writing to the corresponding sparse space
1.D500.0000 to 1.D503.FFFF modifies the scatter/gather map. Reading
either space reads the scatter/gather map.
The register’s format and contents are:
06 05 0009 0821 20 19 1829 28 27 26 25 24 23 2231 30
MR−0073−93RAGS
P
E
I
A
N
V
T
L
T
O
D
B
E
S
B
E
T
E
R
T
P
E
T
C
R
X
2
K
D
B
F
S
E
O
INT MASKUU 000
Bits Access Init. Description
5:0 R 0 TURBOchannel interrupt mask for the option slots
(0=Enabled, 1=Disabled)
8:6 R 0 Read as zero
18:9 UNP Reserved
19 R 0 Second error occured
20 R 0 DMA buffer error (over/under flow)
21 R 0 DMA cross 2K boundary
22 R 0 TURBOchannel reset in progress (status only)
23 R 0 TURBOchannel parity error
24 R 0 DMA tag error
25 R 0 Single-bit error on I/O write or DMA read operation
26 R 0 Double-bit error on I/O write or DMA read operation
27 R 0 TURBOchannel timeout on I/O request
28 R 0 DMA block too long (exceeds 128 LW limit)
29 R 0 Invalid I/O address
30 R 0 Scatter/gather invalid on DMA
TURBOchannel I/O Registers 3–15