Instruction manual

3.3 TURBOchannel Interface Registers (400/500/600/700/800/900
Models)
All CSRs are quadword-aligned but use only the first longword of the quadword.
Note
The status of unused bits in the CSRs is UNDEFINED and must be
masked out by software.
All addresses are dense space addresses, except where dense and sparse space do
not map to the same register. To generate the sparse space equivalents of dense
pace addresses, set bit [28] and shift bits [27:2] left by one, dropping any overflow
bits.
The TURBOchannel interface registers of 400/500/600/700/800/900 models reside
in addresses 1.C200.000 through 1.D503.FFFF.
The total memory allocated to the TURBOchannel interface registers is 64 MB
(32 MB dense space + 32 MB sparse space). Table 10 lists the 400/500/600/700
/800/900 models’ TURBOchannel interface address map.
Table 10 TURBOchannel Control and Status Registers (400/500/600/700/800
/900) Models
Start
Address
End
Address Size Register Access
Discussed
In
Dense space
1.C200.0000 1.C200.0003 4 B IOSLOT register R/W* Section 3.3.1
1.C200.0004 1.C200.0007 Reserved
1.C200.0008 1.C200.000B 4 B TCCONFIG register R/W* Section 3.3.2
1.C200.000C 1.C200.000F Reserved
1.C200.0010 1.C200.0013 4 B FADR register R/WU* Section 3.3.3
1.C200.0014 1.C200.0017 Reserved
1.C200.0018 1.C200.001B 4 B TCEREG register R/WU* Section 3.3.4
1.C200.001C 1.C21F.FFFF Reserved
1.C200.0020 1.C200.0023 4 B IOSLOT register
(alternate address)
R/W* Section 3.3.1
1.C220.0000 1.C227.FFFF 512
KB
Memory configuration
registers
R/W Section 4.1
1.C228.0000 1.C23F.FFFF Reserved
1.C240.0000 1.C240.0003 4 B Interrupt mask register R Section 3.3.6
1.C240.0004 1.C25F.FFFF Reserved
1.C260.0000 1.C260.0003 4 B Interrupt mask register RC Section 3.3.6
1.C260.0004 1.C27F.FFFF Reserved
(continued on next page)
3–8 TURBOchannel I/O Registers