Instruction manual

3.2.3 Memory Configuration Register (MCR)—1.E000.0010
The following sections discusss:
• MCR use and format (Section 3.2.3.1)
• Memory configuring using the MCR (Section 3.2.3.2)
3.2.3.1 MCR Use and Format
This register specifies memory SIMM sizes. It is accessible by the console and by
the operating system through both I/O read and write operations.
The register’s format and contents are:
03 02 01 0031
MR−0067−93RAGS
SS
PP
S
2
P
31
S
P
0
XXXXX
04
Bit Access Description
0 R SIMMPAIR0 SIZE. When clear, the SIMMPAIR0 SIZE is 16 MB; when
set, the SIMMPAIR0 SIZE is 64 MB. SIMMPAIR0 consists of SIMM0 and
SIMM1.
1 R SIMMPAIR1 SIZE. When clear, the SIMMPAIR1 SIZE is 16 MB; when set
, the SIMMPAIR1 SIZE is 64 MB. SIMMPAIR1 consists of SIMM2 and
SIMM3.
2 R SIMMPAIR2 SIZE. When clear, the SIMMPAIR2 SIZE is 16 MB; when
set, the SIMMPAIR2 SIZE is 64 MB. SIMMPAIR2 consists of SIMM4 and
SIMM5.
3 R SIMMPAIR3 SIZE. When clear, the SIMMPAIR3 SIZE is 16 MB; when
set, the SIMMPAIR3 SIZE is 64 MB. SIMMPAIR3 consists of SIMM6 and
SIMM7.
3.2.3.2 Memory Configuring Using the MCR
The 300 models support two types of memory SIMMs:
• 2Mx36 (8MB) SIMM using 1Mx4 DRAMs.
• 8Mx36 (32MB) SIMM using 4Mx4 DRAMs.
Memory is built using pairs of identically sized SIMMs. The larger SIMM pairs
must be installed in the lower-numbered slots. Hardware maps these SIMMs
automatically. However, firmware and the operating system must ascertain how
memory has been mapped.
The Serial ROM code, which executes first, ascertains the size of memory and
passes this information to the console firmware. Console firmware performs
further memory testing and sets up a bitmap for every valid page in memory.
This information, as well as memory size (placed in the MCR), are available to
the operating system.
TURBOchannel I/O Registers 3–5