Instruction manual

2.5.2 Bus Interface Unit Control Register (BIU_CTL)
The BIU_CTL register is internal to the DECchip 21064 CPU. Only 36 bits of
this 64-bit control register are used during normal system operation. 300 model
register bit settings differ from 400/500/600/700/800/900 register bit settings.
In 300 models, the bits are set:
07 06 05 04 03 02 01 0011 10 09 0815 14 13 1221 20 19 1829 17 1628 27 26 25 24 23 2231 3034 33 3236 35
01110 1000000 X000 000000000111111001100
BC_WE_CTL<15:01>
BC_SIZE
BAD_TCP
BC_PA_DIS
BAD_DP
BC_EN
ECC
OE
BC_FHIT
BC_RD_SPD
BC_WR_SPD
MR−0062−93RAGS
In 400/500/600/700/800/900 models, the bits are set:
07 06 05 04 03 02 01 0011 10 09 0815 14 13 1221 20 19 1829 17 1628 27 26 25 24 23 2231 3034 33 3236 35
01110 0000010 X000 000000010010101011010
BC_WE_CTL<15:01>
BC_SIZE
BAD_TCP
BC_PA_DIS
BAD_DP
BC_EN
ECC
OE
BC_FHIT
BC_RD_SPD
BC_WR_SPD
MR−0063−93RAGS
The BIU_CTL fields have the following meanings.
Position Field Function
0 BCEN Set. Enables the Bcache.
1 ECC Clear in 300 models: causes the CPU to expect parity on its
check pins. Set in 400/500/600/700/800/900 models: causes
the CPU to expect ECC on its check pins.
2 OE (output
enable)
Set. Causes the chip enable/output enable (CEOE) lines to
look like OE lines.
3 BC_FHIT Clear. Prevents forced hits.
7:4 BC_RD_SPD 4-bit field. Clear in 300 models: indicates a 4-cycle Bcache
read. Set in 400/500/600/700/800/900 models: indicates a
5-cycle Bcache read.
11:8 BC_WR_SPD 4-bit field. Clear in 300 models: indicates a 4-cycle Bcache
write. Set in 400/500/600/700/800/900 models: indicates a
5-cycle Bcache write.
27:13 BC_WE_CTL 15-bit field. Set in 300 models: causes a 2-cycle Bcache write.
Clear in 400/500/600/700/800/900 models.
30:28 BC_SIZE 3-bit field. Clear in 300 models: indicates a 256 KB Bcache.
Set in 400/500/600/700/800/900 models: indicates a 512 KB
Bcache.
Memory and I/O Addressing 2–11