Instruction manual

3.3.9 TURBOchannel Reset Register (TCRESET)—1.C2A0.0000 ......... 3–19
4 Address ASIC Registers (400/500/600/700/800/900 Models)
4.1 Memory Configuration Registers ................................ 4–2
4.1.1 Operation . . . ............................................ 4–2
4.1.2 Boot Time. . . ............................................ 4–3
4.1.3 Improper Configuration .................................... 4–4
4.1.4 Disabling Memory ........................................ 4–4
4.2 Victim Address Register and Counter Register (VAR/VACR) ........... 4–6
4.2.1 Initialization ............................................ 4–6
4.2.2 Writing the VACR ........................................ 4–6
4.2.3 Reading the VAR ......................................... 4–6
5 Scatter/Gather (Virtual DMA) RAMs (400/500/600/700/800/900 Models)
5.1 Scatter/Gather Register Map ................................... 5–1
5.2 Organization . . . ............................................ 5–2
5.3 Writing and Reading Scatter/Gather Map Entries ................... 5–3
6 CXTurbo Graphics Subsystem: 300/500 Models
6.1 Comparison of Features . . . .................................... 6–2
6.2 CXTurbo Address Map ........................................ 6–3
6.3 Frame Buffer Control Registers ................................. 6–5
6.4 SFB ASIC Functions ......................................... 6–7
6.4.1 Mode Register ........................................... 6–9
6.4.2 Planemask Register . . . .................................... 6–12
6.4.3 Raster Op Register ........................................ 6–13
6.4.4 PixelMask Register . . . .................................... 6–14
6.4.5 Foreground and Background Registers ........................ 6–14
6.4.6 PixelShift Register ........................................ 6–15
6.4.7 Address Register ......................................... 6–15
6.4.8 DEEP Register ........................................... 6–15
6.4.9 START, BCONT, VIDEO_VALID, ENABLE_INTERRUPT,
CLEAR_INTERRUPT Registers . . ............................ 6–16
6.4.10 Video Timing Registers .................................... 6–16
6.4.10.1 Video Refresh Counter Register ........................... 6–17
6.4.10.2 Video Base Address Register . ............................ 6–17
6.4.10.3 Horizontal Setup Register . . . ............................ 6–18
6.4.10.4 Vertical Timing Parameters Register ....................... 6–18
6.4.11 TCCLK COUNT, VIDCLK_COUNT Registers ................... 6–19
6.5 Bt459 RAMDAC . ............................................ 6–20
6.6 System FEPROM (500 Models) ................................. 6–24
7 IOCTL ASIC and System Registers
7.1 IOCTL Address Map ......................................... 7–3
7.2 System FEPROM ............................................ 7–4
7.3 IOCTL Registers Address Map.................................. 7–5
7.3.1 LANCE DMA Pointer Register (LDP)—1.A004.0020/1.E004.0020 . . . . 7–7
7.3.2 Communication Port 1 Transmit DMA
Pointer—1.A004.0030/1.E004.0030............................ 7–7
iv