Instruction manual

1.6 CPU Differences Among Models
The next table lists CPU differences. Other differences are listed in discussions
of specific subsystems and programming requirements.
Model Clock Rate
Cache
Loop Bus Width Bandwidth Time Comments
300 150 MHz 26.66 ns 64 bits read = 300 MB/s
write = 240 MB/s Require an extra
4-cycle probe
read access
300L 100 MHz 40.00 ns 64 bits read = 200 MB/s
write = 160 MB/s Require an extra
4-cycle probe
read access
300X 175 MHz 28.50 ns 64 bits read = 329 MB/s
write = 224 MB/s Require an extra
4-cycle probe
read access
300LX 125 MHz 32.00 ns 64 bits read = 250 MB/s
write = 200 MB/s Require an extra
4-cycle probe
read access
400 133 MHz 37.50 ns 128 bits 427 MB/s
500 150 MHz 33.33 ns 128 bits 480 MB/s
500X 200 MHz 25.00 ns 128 bits 640 MB/s
600 175 MHz 28.57 ns 128 bits 560 MB/s
700 225 MHz 26.67 ns 128 bits 600 MB/s
800 200 MHz 25.00 ns 128 bits 640 MB/s
900 275 MHz 25.45 ns 128 bits 629 MB/s
Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–19