Instruction manual

SETENV, console service routine, 16–70
SET_TERM_INTR, console service routine, 16–72
SFB ASIC, 6–7 to 6–19
SHOWENV console command, 16–25
Simple frame buffer mode, 6–9
Sparse I/O space
address mapping, A–8
addressing in 300 models, figure, A–3
addressing in 400/500/600/700/800/900 models,
figure, A–3
Sparse/dense space
byte-masked I/O read operation, A–4 to A–5
layout, A–2 to A–3
load and store instructions, A–5
performing read and write operations, A–6 to
A–8
read/write minimum granularity, A–4
required number of read/write transactions,
A–4
SROM sequence in processor initialization, 11–2
START console command, 16–30
START register, SFB ASIC, 6–16
Stipple modes, 6–9
Symbolic addresses, 16–12
SYSROM, sequence in processor initialization,
11–2
System
address register, 7–15
description
300 models, 1–2 to 1–5
400 models, 1–6 to 1–8
500 models, 1–9 to 1–12
600 models, 1–15
800 models, 1–18
600/700 models, 1–13
800/900 models, 1–16
FEPROM (500 Models), 6–24
firmware entry, 14–9 to 14–13
boot, 14–9
halt, 14–12
reentry control, 14–13
restart, 14–9
interrupt mask register, 7–15
interrupt register, 7–12 to 7–15
ROM format, 13–3 to 13–6
ROM header
components, 13–4 to 13–5
figure, 13–4
support register, 7–10 to 7–11
T
TCCONFIG, see TURBOchannel configuration
register
TCEREG, see TURBOchannel error register
TCRESET, see TURBOchannel reset register
TCSR, see TURBOchannel control and status
register
Tag space, Bcache, 2–12
TCCLK COUNT register, SFB ASIC counter
clocks, 6–19
TERMCTL, console service routine, 16–73
TEST console command, 16–30
Testing, error insertion, 10–14
Timeout, I/O, 9–6
TRIGGER keyword, 16–23
TURBOchannel
algorithm for sizing option slots, 18–1
configuration register
400/500/600/800 models, 3–12
400/500/600/700/800/900 models, 3–12
control and status register
300 models, 3–4
device configuration table, 15–6 to 15–9
figure, 15–6
DMA arbitration
300 models, 9–5
400/500/600/700/800/900 models, 9–6
DMA size, 9–5
dual SCSI
address map, 8–2
ASIC register map, 8–3
DMA buffers, 8–14
internal registers, 8–3 to 8–11
NCR 53C94 registers (300/400/500 models),
8–12
NCR 53CF94-2 registers (600/700/800/900
models), 8–13
error register
400/500/600/700/800/900 models, 3–14
interface bit decode map, 2–7 to 2–8
interface registers
memory configuration registers(400/500/600
/700/800/900 models), 4–2 to 4–5
400/500/600/800 models
TURBOchannel configuration register,
3–12
400/500/600/700/800/900 models, 3–8 to
3–19
failing address register, 3–13
I/O slot configuration register, 3–10 to
3–11
interrupt mask register, 3–15 to 3–16
interrupt register, 3–17 to 3–18
TURBOchannel configuration register,
3–12
TURBOchannel error register, 3–14
TURBOchannel reset register, 3–19
option ROM base addresses, 18–1
reset register
400/500/600/700/800/900 models, 3–19
system-specific usage, 9–5 to 9–7
Index–7