Instruction manual

Address Mapping in Sparse I/O Space:
The user shifts bits <26:2> to <27:3>, sets bit <28>, and manipulates bit <2>
accordingly.
• To read the register through sparse I/O space, issue an LDL command to the
longword at this address:
03 02 01 0029 28 273133 32
MR−0116−93RAGS
0 1 7 1 420005 0 XX
: Longword PA
04
0
• To write to the register through sparse I/O space:
Write any combination of 1-4 bytes in this register, by issuing an STQ
command, which causes the the data to be written to the following
address:
03 02 01 0029 28 273133 32
MR−0116−93RAGS
0 1 7 1 420005 0 XX
: Longword PA
04
0
It also causes byte mask to be written to bits<3:0> of the following:
03 02 01 0029 28 273133 32
0 1 7 1 420005 1 XX
: Longword PA
04
0
MR−0115−93RAGS
Write exactly one longword to this register by issuing an STL instruction,
writing the data to this longword address:
03 02 01 0029 28 273133 32
MR−0116−93RAGS
0 1 7 1 420005 0 XX
: Longword PA
04
0
Do not write to this longword address:
03 02 01 0029 28 273133 32
0 1 7 1 420005 1 XX
: Longword PA
04
0
MR−0115−93RAGS
A–8 Dense and Sparse Space