Instruction manual

3. Clear byte-mask-enable bit in SSR in IOCTL to disable byte-masking of
future I/O Reads.
A.5 Effect of Load and Store Instructions in Dense and Sparse
Space
Table 75 lists the effect of load and store instructions in dense I/O space; Table 76
lists the effect of load and store instructions in sparse I/O space.
Table 75 Effect of Load and Store Instructions in Dense Space
Instr. Low Longword High Longword
LDL Low longword of quadword being
addressed is sign extended and
loaded
1
High longword of quadword being addressed
is sign extended and loaded
1
LDQ Quadword is loaded NA
STL Less significant longword
(<31:0>) of CPU register is
stored to low longword of
quadword being addressed
Less significant longword (<31:0>) of CPU
register is stored to high longword of
quadword being addressed
STQ Quadword is stored NA
1
Both high and low longwords of the quadword are read.
Table 76 Effect of Load and Store Instructions in Sparse Space
Instr. Low Longword High Longword
LDL Low longword of quadword being addressed is
sign extended and loaded
NA
LDQ Low longword of quadword being addressed is
is loaded into both more significant longword
(<63:32>) and less significant longword (<31:0>)
of CPU register
NA
STL Less significant longword (<31:0>) of CPU
register is stored in low longword of quadword
being addressed
NA
STQ One to four bytes of less significant longword
(<31:0>) of CPU register are stored using byte
mask in more significant longword (<63:32>) of
the CPU register
NA
A.6 Mapping I/O Addresses
This section discusses how to perform read and write operations from and
to I/O registers (Section A.6.1) and gives an example of I/O address mapping
(Section A.6.2).
Dense and Sparse Space A–5