Instruction manual

A.2 Required Number of Transactions
The number of required system bus transactions to complete a read operation in
dense I/O space differs from the required number in sparse I/O space. Depending
on how you write the operating system and device drivers, you may incur
more software overhead by formatting data for sparse I/O space read and write
operations than by formatting them for dense I/O space write operations.
• I/O Write Operations: The CPU chip sends data out from its write buffers
8 longwords at a time. Since the CPU’s data bus is 4 longwords wide
in 400/500/600/700/800/900 models and 2 longwords wide in 300 models,
write operations through dense I/O space allow the CPU card to issue 4
simultaneous longword writes in 400/500/600/700/800/900 models and 2
simultaneous longword writes in 300 models.
In contrast, write operations through sparse I/O space allow at most 2
simultaneous longword writes in 400/500/600/700/800/900 models and 1
longword write in 300 models.
• I/O Read Operations: You can perform read operations a quadword at a time
through dense I/O space.
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A.3 Minimum Granularity
The minimum granularity of read and write operations in dense I/O space differs
from that of the same operations in sparse I/O space, as shown in Table 74.
Table 74 Minimum Granularity
Function I/O Space Granularity
Read Dense Quadword
Sparse Byte
Write Dense Longword
Sparse Byte
A.4 Byte-Masked I/O Read Operations
The TURBOchannel supports byte-masked I/O reads and writes.
You can perform byte-masked I/O read operations only in sparse space (address
bit <28> set). To perform this operation, the TURBOchannel interface logic
fetches 4 bits from the system support register (SSR bits <3:0> ) located in the
IOCTL ASIC. The interface logic uses these bits as the byte-mask field during the
TURBOchannel address cycle for the read operation.
However, the 4 bits are used for byte-masking only when another bit in the
system support register (SSR bit <4>) is set enabling byte-masking. In order to
perform the byte-masked I/O read operation, the programmer must:
1. Write byte-mask and byte-mask-enable bits in SSR in IOCTL.
2. Perform I/O Read (LDL) in sparse space as described before.
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Although the quadword read operation becomes two longword read operations on the
TURBOchannel, the bandwidth of the read operation through dense I/O space is higher
than it would be through sparse I/O space, only one transaction (rather than two) takes
place on the system bus.
A–4 Dense and Sparse Space