Instruction manual

System components are:

• CPU:

A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KB

data caches, and a 64-KB serial boot ROM. A 64-KB stream holds the

primitive boot code for booting the operating system. Jumpers provide for the

selection of up to seven other streams for diagnostic and other purposes. (The

entire UVPROM is 64 K x 8.)

Section 2.5 discusses CPU registers that must be assigned speciﬁc values at

startup.

• Cache:

A module-level write-back cache, or Bcache, consisting of 2 MB, 32-byte

blocks, Single Bit Correction, Double Bit Detection (SBCDBD) ECC protected.

The cache tags are parity-protected, with separate parity bits for the address

and control sections. (There is only one bit of control, a dirty bit.)

Section 2.6 describes Bcache tag space.

Section 10.1 describes the Bcache as a source of errors and interrupts.

Section 11.2 describes Bcache initialization.

• Scatter/Gather Map:

A 32K-entry scatter/gather map, for virtual DMA. Each entry maps an 8-KB

Alpha AXP/DECchip 21064–AA page. Chapter 5 discusses the scatter/gather

maps.

• Address Path ASIC:

An address path ASIC

• Datapath ASICs

Four datapath ASICs

• Memory Banks:

32 MB-512 MB system memory, SBCDBD ECC protected, consisting of up to

two physical memory banks, each one of which must be populated by eight

SIMMS. Using 1M x 4 DRAMs, the minimum memory size is 32 MB. Using

4M x 4 DRAMs, the maximum memory size is 512 MB.

Section 2.2 gives memory and I/O address spaces; Section 4.1 describes

the format, operation, and proper conﬁguration of Memory Conﬁguration

Registers.

• TURBOchannel Interface:

A 25 MHz TURBOchannel interface for I/O, which is controlled by a

TURBOchannel ASIC. The interface has virtual DMA capability for any

TURBOchannel option, high-speed block I/O write, and parity protection.

Section 3.3 describes TURBOchannel Control and Status Registers.

Section 9.4 discusses TURBOchannel I/O programming.

• TURBOchannel Option Slots:

Three TURBOchannel option slots. Each slot has 128 MB of I/O address

space.

1–14 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP