Instruction manual

Component Address Length Description
Physical address
of PALcode
memory space
+ 98 8 bytes Starting physical address of the PALcode for
this processor.
Physical address
of PALcode
scratch space
+ A0 8 bytes Starting physical address of the PALcode
scratch space.
PALcode revision + A8 8 bytes The PALcode revision is broken up as shown
in Figure 28.
Processor type + B0 8 bytes Identifies the type of processor; field contains
2.
Processor
variation
+ B8 8 bytes Identifies the subtype variation of the
processor. The following table describes
the current variations.
Bit Description
0 (VAX-FP) When set indicates that
the processor supports VAX
floating point instructions.
1 (IEEE-FP) When set, indicates that the
processor supports IEEE
floating point operations and
data types.
63:2 RESERVED
Processor revision + C0 8 bytes Contains the four ASCII characters of this
processor’s revision field.
Processor serial
number
+ C8 16 bytes Full serial number of this processor.
Logout memory
address
+ D8 8 bytes Physical address of machine check.
Logout length + E0 8 bytes Length of machine check logout frame in
bytes.
Halt PCBB + E8 8 bytes The value of the PCBB IPR when a HALT
occurs. The console initializes this field
to point to the processor’s HWPCB in this
per-CPU slot portion of the HWRPB.
Halt PC + F0 8 bytes The value of the PC when a HALT occurs.
Console initialization writes a 0 to this field.
Halt PS + F8 8 bytes The value of the PS when a HALT occurs.
The console initializes this field to 0.
Halt argument
list
+ 100 8 bytes The value of R25 (argument list) when a
processor halt condition is encountered; this
value is cleared to zero at system bootstraps
or secondary processor starts.
Halt return
address list
+ 108 8 bytes The value of R26 (return address) when a
processor halt condition is encountered; this
value is cleared to zero at system bootstraps
or secondary processor starts.
Console 16–41