Instruction manual

10.8 PAL Recovery Algorithms for Selected Errors
The following sections give examples of PAL recovery algorithms for the following
selected errors:
• Bcache tag error on DMA read/WRite (Section 10.8.1)
• Bcache tag parity error on CPU reference, LDxL, STxC (Section 10.8.2)
10.8.1 Bcache Tag Error on DMA Read/Write
DMA write operation tag parity errors may be signalled after data has been
transferred, causing the TCEREG and FADR registers to lock with incorrect data.
The following rules apply to DMA tag errors:
1. A tag parity error on DMA read operations is always recorded correctly; the
contents of the TCEREG and FADR registers are accurate.
2. A tag parity error on a DMA write operation is sometimes recorded correctly.
In particular, if the TCEREG indicates that the error occured as the result of
a DMA write operation, the information in the TCEREG and FADR registers
is accurate.
3. If TCEREG indicates that an I/O operation was in error and IR indicates a
tag parity error, the failure was caused by a DMA write operation, provided
that no second error bit in the IR is set. However, in this case, the contents of
the TCEREG and FADR registers are incorrect.
ABOX_CTL<MCHK_EN> = 0; turn off machine checks
ABOX_CTL<DC_ENA> = 0;
if ( block already flushed to mem, tag at index doesn’t match
address in TC register )
or
( tag matches, and dirty bit is set )
or
(isr.seo = 1 second error occurred )
then begin
build stack
build logout, r=0
mchks on
unlock any remaining error regs
ABOX_CTL<DC_ENA> = 1;
call OS
end
else begin
BIU_CTL<BC_ENA> = 0;
read new copy from memory,
causing new tag to be written
tmp = (err_adr);
turn Bcache on again
BIU_CTL<BC_ENA> = 1;
enable DCache again
ABOX_CTL<DC_EN> = 1;
clear errors out
tmp := BIU_ADDR;
enable mchks again
ABOX_CTL<MCHK_EN> = 1;
ABOX_CTL<DC_ENA> = 1;
call OS
end;
10–16 Hardware Exceptions and Interrupts